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authorRonald G. Minnich <rminnich@gmail.com>2013-03-01 10:18:14 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-06 23:41:42 +0100
commit6bde149d9c56a824eff5db7bb06d7c386fb2be30 (patch)
tree2e7e5254a29d53e2a24f42d723bbac9e66a03af5 /src/mainboard/google/snow/romstage.c
parenta4b802ce866a1f3397f0e93e530bf77e253f60ee (diff)
samsung/exynos5: add display port and framebuffer defines and initialization
These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2570 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/snow/romstage.c')
-rw-r--r--src/mainboard/google/snow/romstage.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 25c0846a07..8de4381d03 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -31,7 +31,6 @@
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/clock_init.h>
-
#include <console/console.h>
#include <arch/stages.h>
@@ -68,6 +67,11 @@ static void initialize_s5p_mshc(void) {
exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
}
+static void graphics(void)
+{
+
+ exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+}
void main(void)
{
struct mem_timings *mem;
@@ -106,6 +110,8 @@ void main(void)
initialize_s5p_mshc();
+ graphics();
+
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);