samsung/exynos5: add display port and framebuffer defines and initialization

These are essential functions for setting up the display port and
framebuffer, and also enable such things as aux channel
communications.  We do some very simple initialization in romstage,
mainly set a GPIO so that the graphics is powering up, but the complex
parts are done in the ramstage. This mirrors the way in which graphics
is done in the x86 size.

I've added a first pass at a real device, and put it in the mainboard
Kconfig, hoping for corrections. Because startup is so complex,
depending on device type, I've created a 'displayport' device that
removes some of the complexity and makes the flow *much* clearer.  You
can actually follow the flow by looking at the code, which is not true
on other implementations. Since display port is perhaps the main port
used on these chips, that's a reasonable compromise. All parameters of
importance are now in the device tree.

Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2570
Tested-by: build bot (Jenkins)

1 files changed, 14 insertions, 0 deletions

diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index 4c88ea8e98..5ad786ef55 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -28,5 +28,19 @@ device domain 0 on
 		device i2c 6 on end # ?
 		device i2c 9 on end # ?
 	end
+	chip cpu/samsung/exynos5-common/displayport
+		register "xres" = "1366"
+		register "yres" = "768"
+		register "bpp" = "16"
+		# complex magic timing!
+		register "clkval_f" = "2"
+		register "upper_margin" = "14"
+		register "lower_margin" = "3"
+		register "vsync" = "5"
+		register "left_margin" = "80"
+		register "right_margin" = "48"
+		register "hsync" = "32"
+		register "lcdbase" = "0x10000000"
+	end
 end
 end