diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-05-15 14:54:07 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 20:08:29 +0200 |
| commit | dc006c1db4fa3606d657c78cc87dc13d056e970d (patch) | |
| tree | 7479203a6e08b0b465a104f64316e687885305f5 /src/mainboard/google/snow/chromeos.c | |
| parent | 08dc3571463d7226068d4a4c19d453859b148957 (diff) | |
ARMv7: De-uboot-ify Exynos5250 GPIO code
The Exynos GPIO code has three different APIs that, unfortunately,
were widely used throughout the code base. This patch is cleaning
up the mess.
Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3643
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/snow/chromeos.c')
| -rw-r--r-- | src/mainboard/google/snow/chromeos.c | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 404ed4aecb..2b830a12ff 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -23,7 +23,6 @@ #include <ec/google/chromeec/ec_commands.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> - #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/gpio.h> @@ -32,18 +31,6 @@ enum { ACTIVE_HIGH = 1 }; -enum { - WP_GPIO = 6, - RECMODE_GPIO = 0, - LID_GPIO = 5, - POWER_GPIO = 3 -}; - -static struct exynos5_gpio_part1 *gpio_pt1 = - (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; -static struct exynos5_gpio_part2 *gpio_pt2 = - (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; - void fill_lb_gpios(struct lb_gpios *gpios) { int count = 0; @@ -51,7 +38,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = EXYNOS5_GPD1; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = s5p_gpio_get_value(&gpio_pt1->d1, WP_GPIO); + gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -67,7 +54,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_GPIO); + gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; @@ -75,7 +62,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[count].port = EXYNOS5_GPX1; gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = - s5p_gpio_get_value(&gpio_pt2->x1, POWER_GPIO); + gpio_get_value(GPIO_X13); // POWER_GPIO strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -92,7 +79,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->count = count; printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); - } int get_developer_mode_switch(void) @@ -105,7 +91,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!s5p_gpio_get_value(&gpio_pt1->y1, RECMODE_GPIO)) + if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO return 1; ec_events = google_chromeec_get_events_b(); |