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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:43:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:47:22 +0200
commit4d6ad838e77ad37749f11a4013a1d879e6286fee (patch)
tree475cfdfd1652a13deabb611d337fdf79fcd43605 /src/mainboard/google/smaug/romstage.c
parentfd49d6faf98eb45006a20869da798558cea9606e (diff)
google/smaug: add new mainboard
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/smaug/romstage.c')
-rw-r--r--src/mainboard/google/smaug/romstage.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c
new file mode 100644
index 0000000000..5229a9ffc2
--- /dev/null
+++ b/src/mainboard/google/smaug/romstage.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <device/i2c.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/romstage.h>
+
+#include "gpio.h"
+#include "pmic.h"
+
+static const struct pad_config padcfgs[] = {
+ /* AP_SYS_RESET_L - active low*/
+ PAD_CFG_GPIO_OUT1(SDMMC1_DAT0, PINMUX_PULL_UP),
+ /* WP_L - active low */
+ PAD_CFG_GPIO_INPUT(GPIO_PK2, PINMUX_PULL_NONE),
+ /* BTN_AP_PWR_L - active low */
+ PAD_CFG_GPIO_INPUT(BUTTON_POWER_ON, PINMUX_PULL_UP),
+ /* BTN_AP_VOLD_L - active low */
+ PAD_CFG_GPIO_INPUT(BUTTON_VOL_DOWN, PINMUX_PULL_UP),
+ /* BTN_AP_VOLU_L - active low */
+ PAD_CFG_GPIO_INPUT(SDMMC1_DAT1, PINMUX_PULL_UP),
+};
+
+void romstage_mainboard_init(void)
+{
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+}
+
+void mainboard_configure_pmc(void)
+{
+}
+
+void mainboard_enable_vdd_cpu(void)
+{
+ /* VDD_CPU is already enabled in bootblock. */
+}