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authorSubrata Banik <subrata.banik@intel.com>2020-11-27 00:34:52 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-12-01 07:49:58 +0000
commit0f044a50074d50dea18a73ffd2683b3860c205e2 (patch)
treeb28f3be5124f02c303accf9eadc58d2d16700bc1 /src/mainboard/google/slippy
parentae81d59ecaf050f7e14adb136560e993a98164cf (diff)
mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte) TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
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