google/slippy: clean up NGI and move to libgfxinit

- remove old, buggy NGI code from falco/peppy variants
- remove superfluous INTEL_DP/INTEL_DDI configs, since already
selected by northbridge/haswell
- always use libgfxinit when use native init config selected
- enable NGI/libgfxinit for all slippy variants

The reset of the old Haswell NGI code will be cleaned up in
a subsequent patchset.

Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init
using SeaBIOS and Tianocore payloads on peppy, wolf variants

Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18824
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

8 files changed, 0 insertions, 828 deletions

diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc
index aee33f9188..38d27a4ceb 100644
--- a/src/mainboard/google/slippy/variants/falco/Makefile.inc
+++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc
@@ -13,8 +13,6 @@
 ## GNU General Public License for more details.
 ##
 
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
-
 ## DIMM SPD for on-board memory
 SPD_BIN = $(obj)/spd.bin
 
diff --git a/src/mainboard/google/slippy/variants/falco/gma.c b/src/mainboard/google/slippy/variants/falco/gma.c
deleted file mode 100644
index 19f467c8de..0000000000
--- a/src/mainboard/google/slippy/variants/falco/gma.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <delay.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <edid.h>
-#include <drivers/intel/gma/i915.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <variant/mainboard.h>
-
-/*
- * Here is the rough outline of how we bring up the display:
- *  1. Upon power-on Sink generates a hot plug detection pulse thru HPD
- *  2. Source determines video mode by reading DPCD receiver capability field
- *     (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
- *     0000Dh).
- *  3. Sink replies DPCD receiver capability field.
- *  4. Source starts EDID read thru I2C-over-AUX.
- *  5. Sink replies EDID thru I2C-over-AUX.
- *  6. Source determines link configuration, such as MAX_LINK_RATE and
- *     MAX_LANE_COUNT. Source also determines which type of eDP Authentication
- *     method to use and writes DPCD link configuration field (DPCD 00100h to
- *     0010Ah) including eDP configuration set (DPCD 0010Ah).
- *  7. Source starts link training. Sink does clock recovery and equalization.
- *  8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
- *  9. Sink replies DPCD link status field. If main link is not stable, Source
- *     repeats Step 7.
- * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
- *     parameters and recovers stream clock.
- * 11. Source sends video data.
- */
-
-/* how many bytes do we need for the framebuffer?
- * Well, this gets messy. To get an exact answer, we have
- * to ask the panel, but we'd rather zero the memory
- * and set up the gtt while the panel powers up. So,
- * we take a reasonable guess, secure in the knowledge that the
- * MRC has to overestimate the number of bytes used.
- * 8 MiB is a very safe guess. There may be a better way later, but
- * fact is, the initial framebuffer is only very temporary. And taking
- * a little long is ok; this is done much faster than the AUX
- * channel is ready for IO.
- */
-#define FRAME_BUFFER_BYTES (8*MiB)
-/* how many 4096-byte pages do we need for the framebuffer?
- * There are hard ways to get this, and easy ways:
- * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
- * on this chip (and in fact every Intel graphics chip we've seen).
- */
-#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
-
-static int i915_init_done = 0;
-
-/* fill the palette. */
-static void palette(void)
-{
-	int i;
-	unsigned long color = 0;
-
-	for(i = 0; i < 256; i++, color += 0x010101){
-		gtt_write(_LGC_PALETTE_A + (i << 2),color);
-	}
-}
-
-void mainboard_train_link(struct intel_dp *intel_dp)
-{
-	u8 read_val;
-	u8 link_status[DP_LINK_STATUS_SIZE];
-
-	gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
-	gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
-
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-	intel_dp_get_lane_count(intel_dp, &read_val);
-	intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
-	intel_dp_get_link_status(intel_dp, link_status);
-
-	gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
-
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-	intel_dp_get_link_status(intel_dp, link_status);
-	intel_dp_get_lane_align_status(intel_dp, &read_val);
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-}
-
-#define TEST_GFX 0
-
-#if TEST_GFX
-static void test_gfx(struct intel_dp *dp)
-{
-	int i;
-
-	/* This is a sanity test code which fills the screen with two bands --
-	   green and blue. It is very useful to ensure all the initializations
-	   are made right. Thus, to be used only for testing, not otherwise
-	*/
-	for (i = 0; i < (dp->edid.va - 4); i++) {
-		u32 *l;
-		int j;
-		u32 tcolor = 0x0ff;
-		for (j = 0; j < (dp->edid.ha-4); j++) {
-			if (j == (dp->edid.ha/2)) {
-				tcolor = 0xff00;
-			}
-			l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
-			memcpy(l,&tcolor,sizeof(tcolor));
-		}
-	}
-}
-#else
-static void test_gfx(struct intel_dp *dp) {}
-#endif
-
-
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
-{
-	u32 ddi_pll_sel = 0;
-
-	switch (intel_dp->link_bw) {
-	case DP_LINK_BW_1_62:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
-		break;
-	case DP_LINK_BW_2_7:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
-		break;
-	case DP_LINK_BW_5_4:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
-		break;
-	default:
-		printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
-		return;
-	}
-
-	gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
-}
-
-int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
-{
-	int i;
-	int edid_ok;
-	int pixels = FRAME_BUFFER_BYTES/64;
-
-	void runio(struct intel_dp *dp);
-
-	dp->gen = 8; // This is gen 8 which we believe is Haswell
-	dp->is_haswell = 1;
-	dp->DP = 0x2;
-	/* These values are used for training the link */
-	dp->lane_count = 2;
-	dp->link_bw = DP_LINK_BW_2_7;
-	dp->pipe = PIPE_A;
-	dp->port = PORT_A;
-	dp->plane = PLANE_A;
-	dp->clock = 160000;
-	dp->pipe_bits_per_pixel = 32;
-	dp->type = INTEL_OUTPUT_EDP;
-	dp->output_reg = DP_A;
-	/* observed from YABEL. */
-	dp->aux_clock_divider = 0xe1;
-	dp->precharge = 3;
-
-	/* 1. Normal mode: Set the first page to zero and make
-	   all GTT entries point to the same page
-	   2. Developer/Recovery mode: We do not zero out all
-	   the pages pointed to by GTT in order to avoid wasting time */
-        if (init_fb){
-		set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096);
-		memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
-        } else {
-                set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
-                memset((void*)dp->graphics, 0, 4096);
-        }
-
-	dp->address = 0x50;
-
-	if ( !intel_dp_get_dpcd(dp) )
-		goto fail;
-
-	intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
-	for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
-		if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
-					0x50, &dp->rawedid[i]) < 0)
-			break;
-		dp->edidlen++;
-	}
-
-	edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
-	printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
-
-	compute_display_params(dp);
-
-	intel_ddi_set_pipe_settings(dp);
-
-	runio(dp);
-
-	palette();
-
-	pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4;
-	printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va);
-
-	test_gfx(dp);
-
-	set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
-	i915_init_done = 1;
-	return i915_init_done;
-
-fail:
-	printk(BIOS_SPEW, "Graphics could not be started;");
-	printk(BIOS_SPEW, "Returning.\n");
-	return 0;
-}
diff --git a/src/mainboard/google/slippy/variants/falco/i915io.c b/src/mainboard/google/slippy/variants/falco/i915io.c
deleted file mode 100644
index d51cb43c52..0000000000
--- a/src/mainboard/google/slippy/variants/falco/i915io.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-/* This code was originally generated using an i915tool program. It has been
- * improved by hand.
- */
-
-#include <stdint.h>
-#include <console/console.h>
-#include <delay.h>
-#include <drivers/intel/gma/i915.h>
-#include <arch/io.h>
-#include <variant/mainboard.h>
-
-/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
-void runio(struct intel_dp *dp);
-
-void runio(struct intel_dp *dp)
-{
-	u8 read_val;
-
-	intel_dp_wait_panel_power_control(0xabcd0008);
-
-	/* vbios spins at this point. Some haswell weirdness? */
-	intel_dp_wait_panel_power_control(0xabcd0008);
-
-	/* This should be a function like intel_panel_enable_backlight
-	   However, we are not sure how the value 0x3a9 comes up.
-	   It has to do something with PWM frequency */
-	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
-
-	gtt_write(DEIIR,0x00008000);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-
-	intel_dp_sink_dpms(dp, 0);
-
-	intel_dp_get_max_downspread(dp, &read_val);
-
-	intel_dp_set_m_n_regs(dp);
-
-	intel_dp_set_resolution(dp);
-
-	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
-	gtt_write(PIPECONF(dp->transcoder),0x00000000);
-	gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
-
-	mainboard_set_port_clk_dp(dp);
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
-	gtt_write(DEIIR,0x00000080);
-
-	gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
-	gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
-
-	intel_dp_wait_panel_power_control(0xabcd000a);
-
-	/* what is this doing? Not sure yet. */
-	intel_dp_i2c_write(dp, 0x0);
-	intel_dp_i2c_read(dp, &read_val);
-	intel_dp_i2c_write(dp, 0x04);
-	intel_dp_i2c_read(dp, &read_val);
-	intel_dp_i2c_write(dp, 0x7e);
-	intel_dp_i2c_read(dp, &read_val);
-
-	/* this needs to be a call to a function */
-	gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
-	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
-	gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
-
-	/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
-	gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a);
-	gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a);
-
-	intel_dp_set_bw(dp);
-	intel_dp_set_lane_count(dp);
-
-	mainboard_train_link(dp);
-
-	/* need a function: intel_ddi_set_tp or similar */
-	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
-	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
-
-	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
-
-	/* some of this is not needed. */
-	gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
-
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(DEIIR,0x00000000);
-	gtt_write(DEIIR,0x00008000);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
-
-	gtt_write(DEIIR,0x00000080);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-
-	gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
-
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(DEIIR,0x00000000);
-}
diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h b/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h
deleted file mode 100644
index 6329a27805..0000000000
--- a/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __MAINBOARD_H_
-#define __MAINBOARD_H_
-void mainboard_train_link(struct intel_dp *intel_dp);
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
-
-#endif
diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc
index 576af04a1b..9d19818046 100644
--- a/src/mainboard/google/slippy/variants/peppy/Makefile.inc
+++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc
@@ -13,8 +13,6 @@
 ## GNU General Public License for more details.
 ##
 
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
-
 ## DIMM SPD for on-board memory
 SPD_BIN = $(obj)/spd.bin
 
diff --git a/src/mainboard/google/slippy/variants/peppy/gma.c b/src/mainboard/google/slippy/variants/peppy/gma.c
deleted file mode 100644
index afdb4d6b31..0000000000
--- a/src/mainboard/google/slippy/variants/peppy/gma.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <delay.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <edid.h>
-#include <drivers/intel/gma/i915.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <variant/mainboard.h>
-
-/*
- * Here is the rough outline of how we bring up the display:
- *  1. Upon power-on Sink generates a hot plug detection pulse thru HPD
- *  2. Source determines video mode by reading DPCD receiver capability field
- *     (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
- *     0000Dh).
- *  3. Sink replies DPCD receiver capability field.
- *  4. Source starts EDID read thru I2C-over-AUX.
- *  5. Sink replies EDID thru I2C-over-AUX.
- *  6. Source determines link configuration, such as MAX_LINK_RATE and
- *     MAX_LANE_COUNT. Source also determines which type of eDP Authentication
- *     method to use and writes DPCD link configuration field (DPCD 00100h to
- *     0010Ah) including eDP configuration set (DPCD 0010Ah).
- *  7. Source starts link training. Sink does clock recovery and equalization.
- *  8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
- *  9. Sink replies DPCD link status field. If main link is not stable, Source
- *     repeats Step 7.
- * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
- *     parameters and recovers stream clock.
- * 11. Source sends video data.
- */
-
-/* how many bytes do we need for the framebuffer?
- * Well, this gets messy. To get an exact answer, we have
- * to ask the panel, but we'd rather zero the memory
- * and set up the gtt while the panel powers up. So,
- * we take a reasonable guess, secure in the knowledge that the
- * MRC has to overestimate the number of bytes used.
- * 8 MiB is a very safe guess. There may be a better way later, but
- * fact is, the initial framebuffer is only very temporary. And taking
- * a little long is ok; this is done much faster than the AUX
- * channel is ready for IO.
- */
-#define FRAME_BUFFER_BYTES (8*MiB)
-/* how many 4096-byte pages do we need for the framebuffer?
- * There are hard ways to get this, and easy ways:
- * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
- * on this chip (and in fact every Intel graphics chip we've seen).
- */
-#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
-
-
-static int i915_init_done = 0;
-
-/* fill the palette. */
-static void palette(void)
-{
-	int i;
-	unsigned long color = 0;
-
-	for(i = 0; i < 256; i++, color += 0x010101){
-		gtt_write(_LGC_PALETTE_A + (i << 2),color);
-	}
-}
-
-void mainboard_train_link(struct intel_dp *intel_dp)
-{
-	u8 read_val;
-	u8 link_status[DP_LINK_STATUS_SIZE];
-
-	gtt_write(DP_TP_CTL(intel_dp->port),
-		  DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
-	gtt_write(DDI_BUF_CTL_A,
-		  DDI_BUF_CTL_ENABLE|
-		  DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
-
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp,
-				      DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
-				      DP_SYMBOL_ERROR_COUNT_BOTH);
-
-	intel_dp_set_training_lane0(intel_dp,
-				    DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
-	intel_dp_get_link_status(intel_dp, link_status);
-
-	gtt_write(DP_TP_CTL(intel_dp->port),
-		  DP_TP_CTL_ENABLE |
-		  DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
-
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
-				      DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-	intel_dp_get_link_status(intel_dp, link_status);
-	intel_dp_get_lane_align_status(intel_dp, &read_val);
-	intel_dp_get_training_pattern(intel_dp, &read_val);
-	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
-				      DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
-}
-
-/* This variable controls whether the test_gfx function below puts up
- * color bars or not. In previous revs we ifdef'd the test_gfx function out
- * but it's handy, especially when using a JTAG debugger
- * to be able to enable and disable a test graphics.
- */
-int show_test = 0;
-
-static void test_gfx(struct intel_dp *dp)
-{
-	int i;
-
-	if (!show_test)
-		return;
-	/* This is a sanity test code which fills the screen with two bands --
-	   green and blue. It is very useful to ensure all the initializations
-	   are made right. Thus, to be used only for testing, not otherwise
-	*/
-
-	for (i = 0; i < (dp->edid.mode.va - 4); i++) {
-		u32 *l;
-		int j;
-		u32 tcolor = 0x0ff;
-		for (j = 0; j < (dp->edid.mode.ha-4); j++) {
-			if (j == (dp->edid.mode.ha/2)) {
-				tcolor = 0xff00;
-			}
-			l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
-			memcpy(l,&tcolor,sizeof(tcolor));
-		}
-	}
-	printk(BIOS_SPEW, "sleep 10\n");
-	delay(10);
-}
-
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
-{
-	u32 ddi_pll_sel = 0;
-
-	switch (intel_dp->link_bw) {
-	case DP_LINK_BW_1_62:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
-		break;
-	case DP_LINK_BW_2_7:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
-		break;
-	case DP_LINK_BW_5_4:
-		ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
-		break;
-	default:
-		printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
-		return;
-	}
-
-	gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
-}
-
-int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
-{
-	int i;
-	int edid_ok;
-	int pixels = FRAME_BUFFER_BYTES/64;
-
-	gtt_write(PCH_PP_CONTROL,0xabcd000f);
-	delay(1);
-
-	void runio(struct intel_dp *dp);
-	/* hard codes -- stuff you can only know from the mainboard */
-	dp->gen = 8; // This is gen 8 which we believe is Haswell
-	dp->is_haswell = 1;
-	dp->DP = 0x2;
-	dp->pipe = PIPE_A;
-	dp->port = PORT_A;
-	dp->plane = PLANE_A;
-	dp->pipe_bits_per_pixel = 24;
-	dp->type = INTEL_OUTPUT_EDP;
-	dp->output_reg = DP_A;
-	/* observed from YABEL. */
-	dp->aux_clock_divider = 0xe1;
-	dp->precharge = 3;
-
-	/* 1. Normal mode: Set the first page to zero and make
-	   all GTT entries point to the same page
-	   2. Developer/Recovery mode: Set up a tasteful color
-	      so people know we are alive. */
-        if (init_fb || show_test) {
-                set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase,
-					4096);
-		memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
-        } else {
-		set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
-                memset((void*)dp->graphics, 0, 4096);
-        }
-
-	dp->address = 0x50;
-
-	if ( !intel_dp_get_dpcd(dp) )
-		goto fail;
-
-	intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
-	for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
-		if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
-					0x50, &dp->rawedid[i]) < 0)
-			break;
-		dp->edidlen++;
-	}
-
-	edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
-
-	printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
-
-	compute_display_params(dp);
-
-	printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
-	       dp->edid.mode.pixel_clock, dp->edid.link_clock);
-
-	intel_ddi_set_pipe_settings(dp);
-
-	runio(dp);
-
-	palette();
-
-	pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4;
-	printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va);
-	test_gfx(dp);
-
-	set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
-	i915_init_done = 1;
-	return 1;
-
-fail:
-	printk(BIOS_SPEW, "Graphics could not be started;");
-	/* unclear we will *ever* want to do this. */
-	if (0){
-		printk(BIOS_SPEW, "Turn off power and wait ...");
-		gtt_write(PCH_PP_CONTROL,0xabcd0000);
-		udelay(600000);
-		gtt_write(PCH_PP_CONTROL,0xabcd000f);
-	}
-	printk(BIOS_SPEW, "Returning.\n");
-	return 0;
-}
diff --git a/src/mainboard/google/slippy/variants/peppy/i915io.c b/src/mainboard/google/slippy/variants/peppy/i915io.c
deleted file mode 100644
index 6cf2d0ed27..0000000000
--- a/src/mainboard/google/slippy/variants/peppy/i915io.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#include <stdint.h>
-#include <console/console.h>
-#include <delay.h>
-#include <drivers/intel/gma/i915.h>
-#include <arch/io.h>
-#include <variant/mainboard.h>
-
-void runio(struct intel_dp *dp,  int verbose);
-void runio(struct intel_dp *dp,  int verbose)
-{
-	u8 read_val;
-	gtt_write(DDI_BUF_CTL_A,
-		  DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
-		  |0x00000091);
-
-	intel_prepare_ddi();
-
-	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
-
-	gtt_write(DEIIR,0x00008000);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-	gtt_write(DSPSTRIDE(dp->plane), dp->stride);
-	gtt_write(DSPADDR(dp->plane), 0x00000000);
-
-	printk(BIOS_SPEW, "DP_SET_POWER");
-
-	intel_dp_sink_dpms(dp, 0);
-
-	intel_dp_set_m_n_regs(dp);
-
-	intel_dp_get_max_downspread(dp, &read_val);
-
-	intel_dp_set_resolution(dp);
-
-	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
-        gtt_write(PIPECONF(dp->transcoder),0x00000000);
-        gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
-
-	mainboard_set_port_clk_dp(dp);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-        gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
-
-	gtt_write(DEIIR,0x00000080);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	/* There is some reason we removed these three calls from
-	 * slippy/gma.c -- I dont remember why!! */
-	gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
-	gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
-	gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
-
-	gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
-        gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
-
-	/* what is this doing? Not sure yet. But we don't seem to be
-	 * able to live without it.*/
-	intel_dp_i2c_write(dp, 0x0);
-	intel_dp_i2c_read(dp, &read_val);
-	intel_dp_i2c_write(dp, 0x04);
-	intel_dp_i2c_read(dp, &read_val);
-	intel_dp_i2c_write(dp, 0x7e);
-	intel_dp_i2c_read(dp, &read_val);
-
-	gtt_write(DDI_BUF_CTL_A,
-		  DDI_BUF_IS_IDLE|
-		  DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
-		  |0x00000091);
-
-	gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
-	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
-		  DP_TP_CTL_ENHANCED_FRAME_ENABLE);
-
-	gtt_write(DDI_BUF_CTL_A,
-		  DDI_BUF_CTL_ENABLE|
-		  /* another undocumented setting. Surprised? */ 0x40000 |
-		  DDI_BUF_IS_IDLE|DDI_A_4_LANES|
-		  DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
-		  0x80040091);
-
-	intel_dp_set_bw(dp);
-
-	intel_dp_set_lane_count(dp);
-
-	mainboard_train_link(dp);
-
-	gtt_write(DP_TP_CTL(dp->port),
-		  DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
-		  DP_TP_CTL_LINK_TRAIN_IDLE);
-
-	gtt_write(DP_TP_CTL(dp->port),
-		  DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
-		  DP_TP_CTL_LINK_TRAIN_NORMAL);
-
-	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
-	gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
-
-	/* some of this is not needed. But with a total lack of docs, well ...*/
-	gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
-
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(DEIIR,0x00000000);
-	gtt_write(DEIIR,0x00008000);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
-
-	gtt_write(DEIIR,0x00000080);
-	intel_dp_wait_reg(DEIIR, 0x00000000);
-
-	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
-	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-
-	gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
-
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(SDEIIR,0x00000000);
-	gtt_write(DEIIR,0x00000000);
-
-}
diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h b/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h
deleted file mode 100644
index 6329a27805..0000000000
--- a/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __MAINBOARD_H_
-#define __MAINBOARD_H_
-void mainboard_train_link(struct intel_dp *intel_dp);
-void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
-
-#endif