nb/intel/haswell: Consolidate memory-down SPD handling

Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.

Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 34 insertions, 44 deletions

diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 05b4eb78c5..e808182274 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -6,22 +6,22 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {13, 9, 47, -1};
+	return get_gpios(gpio_vector);
+}
 
-	unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Index 0-2,6 are 4GB config with both CH0 and CH1
-	 * Index 3-5,7 are 2GB config with CH0 only
-	 */
+	   Index 3-5,7 are 2GB config with CH0 only */
 	switch (spd_index) {
 	case 0: case 1: case 2: case 6:
-		memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
-		break;
+		return true;
 	case 3: case 4: case 5: case 7:
-		peid->dimm_channel1_disabled = 3;
+	default:
+		return false;
 	}
 }
 
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index 2e5dee195e..c22e25b897 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -6,20 +6,17 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {13, 9, 47, -1};
+	return get_gpios(gpio_vector);
+}
 
-	unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	/* Limiting to a single dimm for 2GB configuration
-	 * Identified by bit 3
-	 */
-	if (spd_index & 0x4)
-		peid->dimm_channel1_disabled = 3;
-	else
-		memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
+	   Identified by bit 2 */
+	return !(spd_index & 0x4);
 }
 
 const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 12e2714b6d..dd998f00f3 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -9,33 +9,26 @@
 #include "../../onboard.h"
 #include "../../variant.h"
 
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {13, 9, 47, -1};
+	return get_gpios(gpio_vector);
+}
 
-	unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
 	uint32_t board_version = PEPPY_BOARD_VERSION_PROTO;
 	google_chromeec_get_board_version(&board_version);
 	switch (board_version) {
 	case PEPPY_BOARD_VERSION_PROTO:
 		/* Index 0 is 2GB config with CH0 only. */
-		if (spd_index == 0)
-			peid->dimm_channel1_disabled = 3;
-		else
-			memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
-		break;
+		return spd_index != 0;
 
 	case PEPPY_BOARD_VERSION_EVT:
 	default:
 		/* Index 0-3 are 4GB config with both CH0 and CH1.
-		 * Index 4-7 are 2GB config with CH0 only. */
-		if (spd_index > 3)
-			peid->dimm_channel1_disabled = 3;
-		else
-			memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
-		break;
+		   Index 4-7 are 2GB config with CH0 only. */
+		return spd_index <= 3;
 	}
 }
 
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 05e128d87e..95a14a08aa 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -6,22 +6,22 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
-/* Copy SPD data for on-board memory */
-void copy_spd(struct pei_data *peid)
+unsigned int variant_get_spd_index(void)
 {
 	const int gpio_vector[] = {13, 9, 47, -1};
+	return get_gpios(gpio_vector);
+}
 
-	unsigned int spd_index = fill_spd_for_index(peid->spd_data[0], get_gpios(gpio_vector));
-
-	/* Index 0-2, are 4GB config with both CH0 and CH1
-	 * Index 3-5, are 2GB config with CH0 only
-	 */
+bool variant_is_dual_channel(const unsigned int spd_index)
+{
+	/* Index 0-2 are 4GB config with both CH0 and CH1
+	   Index 3-5 are 2GB config with CH0 only */
 	switch (spd_index) {
 	case 0: case 1: case 2:
-		memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN);
-		break;
+		return true;
 	case 3: case 4: case 5:
-		peid->dimm_channel1_disabled = 3;
+	default:
+		return false;
 	}
 }