Add/Combine Haswell Chromebooks using variant board scheme

Combine existing boards google/falco and google/peppy with new
ChromeOS devices leon and wolf, using their common reference board
(slippy) as a base.

Chromium sources used:
firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...]
firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode]
firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...]

Additionally, some minor cleanup/changes were made:
- I2C devices set to use ACPI (vs PCI) mode
- I2C device ACPI entries adjusted as per above
- I2C devices set to use level (vs edge) interrupt triggering
- XHCI finalization enabled in devicetree
- HDA verb entries use simplified macro entry format

Existing google/falco and google/peppy boards will be removed in a
subsequent commit.

Variant setup modeled after google/beltino

Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

9 files changed, 715 insertions, 0 deletions

diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc
new file mode 100644
index 0000000000..0c860bfc80
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES  = Micron_4KTF25664HZ	# 0: 4GB / CH0 + CH1
+SPD_SOURCES += Hynix_HMT425S6AFR6A	# 1: 4GB / CH0 + CH1
+SPD_SOURCES += Samsung_K4B4G1646B	# 2: 4GB / CH0 + CH1
+SPD_SOURCES += Micron_4KTF25664HZ	# 3: 2GB / CH0
+SPD_SOURCES += Hynix_HMT425S6AFR6A	# 4: 2GB / CH0
+SPD_SOURCES += Samsung_K4B4G1646B	# 4: 2GB / CH0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb
new file mode 100644
index 0000000000..7655c412a9
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb
@@ -0,0 +1,130 @@
+chip northbridge/intel/haswell
+	# IGD Displays
+	register "gfx.ndid" = "3"
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+	# Enable eDP Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Disable DisplayPort C Hotplug
+	register "gpu_dp_c_hotplug" = "0x00"
+
+	# Enable HDMI Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "0x06"
+
+	# Set backlight PWM values for eDP
+	register "gpu_cpu_backlight" = "0x00000200"
+	register "gpu_pch_backlight" = "0x04000000"
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "6"		# 500ms (T11+T12)
+	register "gpu_panel_power_up_delay" = "2000"		# 200ms (T3)
+	register "gpu_panel_power_down_delay" = "500"		# 50ms (T10)
+	register "gpu_panel_power_backlight_on_delay" = "10"	# 1ms (T8)
+	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms (T9)
+
+	device cpu_cluster 0 on
+		chip cpu/intel/haswell
+			device lapic 0 on end
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			register "c1_battery" = "2"	# ACPI(C1) = MWAIT(C1E)
+			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_battery" = "9"	# ACPI(C3) = MWAIT(C7S)
+
+			register "c1_acpower" = "2"	# ACPI(C1) = MWAIT(C1E)
+			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_acpower" = "9"	# ACPI(C3) = MWAIT(C7S)
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
+
+		chip southbridge/intel/lynxpoint
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# EC range is 0x800-0x9ff
+			register "gen1_dec" = "0x00fc0801"
+			register "gen2_dec" = "0x00fc0901"
+
+			# EC_SMI is GPIO34
+			register "alt_gp_smi_en" = "0x0004"
+			register "gpe0_en_1" = "0x00000000"
+			# EC_SCI is GPIO36
+			register "gpe0_en_2" = "0x00000010"
+			register "gpe0_en_3" = "0x00000000"
+			register "gpe0_en_4" = "0x00000000"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x1"
+			register "sata_devslp_disable" = "0x1"
+
+			# DTLE DATA / EDGE values
+			register "sata_port0_gen3_dtle" = "0x5"
+			register "sata_port1_gen3_dtle" = "0x5"
+
+			register "sio_acpi_mode" = "1"
+			register "sio_i2c0_voltage" = "0" # 3.3V
+			register "sio_i2c1_voltage" = "0" # 3.3V
+
+			# Force enable ASPM for PCIe Port 1
+			register "pcie_port_force_aspm" = "0x01"
+
+			# Route all USB ports to XHCI per default
+			register "xhci_default" = "1"
+
+			# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+			register "icc_clock_disable" = "0x013c0000"
+
+			device pci 13.0 off end # Smart Sound Audio DSP
+			device pci 14.0 on end # USB3 XHCI
+			device pci 15.0 on end # Serial I/O DMA
+			device pci 15.1 on end # I2C0
+			device pci 15.2 on end # I2C1
+			device pci 15.3 off end # GSPI0
+			device pci 15.4 off end # GSPI1
+			device pci 15.5 off end # UART0
+			device pci 15.6 off end # UART1
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 17.0 off end # SDIO
+			device pci 19.0 off end # GbE
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1d.0 on end # USB2 EHCI
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on
+				chip ec/google/chromeec
+					# We only have one init function that
+					# we need to call to initialize the
+					# keyboard part of the EC.
+					device pnp ff.1 on # dummy address
+					end
+				end
+			end # LPC bridge
+			device pci 1f.2 on end # SATA Controller
+			device pci 1f.3 on end # SMBus
+			device pci 1f.6 on end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c
new file mode 100644
index 0000000000..b043bf52ce
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0283,	// Codec Vendor / Device ID: Realtek ALC283
+	0x10ec0283,	// Subsystem ID
+	0x0000000e,	// Number of jacks (NID entries)
+
+	0x0017ff00,	// Function Reset
+	0x0017ff00,	// Double Function Reset
+	0x000F0000,	// Pad - get vendor id
+	0x000F0002,	// Pad - get revision id
+
+	/* Bits 31:28 - Codec Address */
+	/* Bits 27:20 - NID */
+	/* Bits 19:8 - Verb ID */
+	/* Bits 7:0  - Payload */
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x12) DMIC - interior mobile lid */
+	AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010),
+
+	/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+	// group 1, cap 0
+	// no connector, no jack detect
+	// speaker out, analog
+	// fixed function, internal, Location N/A
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+	/* Pin Complex (NID 0x17) MONO Out - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+	/* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+	/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+	// group2, cap 0
+	// black, jack detect
+	// Mic in, 3.5mm Jack
+	// connector, External left panel
+	AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+	/* Pin Complex (NID 0x1A) LINE1 - Internal Mic */
+	// group 1, cap 1
+	// no connector, no jack detect
+	// mic in, analog connection
+	// Fixed function, internal, Location N/A
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x90a70111),
+
+	/* Pin Complex (NID 0x1B) LINE2 - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+
+	/* Pin Complex (NID 0x1D) PCBeep */
+	// eapd low on ex-amp, laptop, custom enable
+	// mute spkr on hpout
+	// pcbeep en able, checksum
+	// no physical, Internal, Location N/A
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+
+	/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+
+	/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
+	// group2, cap 1
+	// black, jack detect
+	// HPOut, 3.5mm Jack
+	// connector, left panel
+	AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+
+	/* Undocumented settings from Realtek (needed for beep_gen) */
+	/* Widget node 0x20 */
+	0x02050010,
+	0x02040c20,
+	0x0205001b,
+	0x0204081b,
+
+	/* Tuned jack detection */
+	0x02050043,
+	0x0204A614,
+	0x02050047,
+	0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
+	0x01470740,	/* enable speaker out */
+	0x01470c02,	/* set speaker EAPD pin */
+	0x0143b01f,	/* unmute speaker */
+	0x00c37100,	/* unmute mixer nid 0xc input 1 */
+	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..335077cc83
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <onboard.h>
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name(_HID, EisaId("PNP0C0D"))
+		Method(_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+
+		// There is no GPIO for LID, the EC pulses WAKE# pin instead.
+		// There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
+		Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+}
+
+Scope (\_SB.PCI0.I2C0)
+{
+	Device (CTPA)
+	{
+		Name (_HID, "CYAP0000")
+		Name (_DDN, "Cypress Touchpad")
+		Name (_UID, 3)
+		Name (ISTP, 1) /* Touchpad */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x67,                     // SlaveAddress
+				ControllerInitiated,      // SlaveMode
+				400000,                   // ConnectionSpeed
+				AddressingMode7Bit,       // AddressingMode
+				"\\_SB.PCI0.I2C0"        // ResourceSource
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_TRACKPAD_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GWAK (Local0)
+			}
+		}
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
\ No newline at end of file
diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h
new file mode 100644
index 0000000000..fe2b31438d
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef WOLF_GPIO_H
+#define WOLF_GPIO_H
+
+struct pch_lp_gpio_map;
+
+const struct pch_lp_gpio_map mainboard_gpio_map[] = {
+	LP_GPIO_UNUSED,        /* 0: UNUSED */
+	LP_GPIO_UNUSED,        /* 1: UNUSED */
+	LP_GPIO_UNUSED,        /* 2: UNUSED */
+	LP_GPIO_UNUSED,        /* 3: UNUSED */
+	LP_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	LP_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	LP_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	LP_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	LP_GPIO_ACPI_SCI,      /* 8: LTE_WAKE_L_Q */
+	LP_GPIO_INPUT,         /* 9: RAM_ID1 */
+	LP_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	LP_GPIO_UNUSED,        /* 11: UNUSED */
+	LP_GPIO_INPUT_INVERT,  /* 12: TRACKPAD_INT_L (WAKE) */
+	LP_GPIO_INPUT,         /* 13: RAM_ID0 */
+	LP_GPIO_INPUT,         /* 14: EC_IN_RW */
+	LP_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 16: UNUSED */
+	LP_GPIO_UNUSED,        /* 17: UNUSED */
+	LP_GPIO_NATIVE,        /* 18: PCIE_CLKREQ_WLAN# */
+	LP_GPIO_UNUSED,        /* 19: UNUSED */
+	LP_GPIO_UNUSED,        /* 20: UNUSED */
+	LP_GPIO_UNUSED,        /* 21: UNUSED */
+	LP_GPIO_UNUSED,        /* 22: UNUSED */
+	LP_GPIO_UNUSED,        /* 23: UNUSED */
+	LP_GPIO_UNUSED,        /* 24: UNUSED */
+	LP_GPIO_INPUT_INVERT,  /* 25: TOUCH_INT_L (WAKE) */
+	LP_GPIO_UNUSED,        /* 26: UNUSED */
+	LP_GPIO_UNUSED,        /* 27: UNUSED */
+	LP_GPIO_UNUSED,        /* 28: UNUSED */
+	LP_GPIO_UNUSED,        /* 29: UNUSED */
+	LP_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
+	LP_GPIO_NATIVE,        /* 31: NATIVE: ACPRESENT */
+	LP_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
+	LP_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	LP_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	LP_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	LP_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	LP_GPIO_UNUSED,        /* 37: UNUSED */
+	LP_GPIO_UNUSED,        /* 38: UNUSED */
+	LP_GPIO_UNUSED,        /* 39: UNUSED */
+	LP_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	LP_GPIO_UNUSED,        /* 41: UNUSED */
+	LP_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	LP_GPIO_UNUSED,        /* 43: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 44: PP3300_SSD_EN */
+	LP_GPIO_OUT_HIGH,      /* 45: PP3300_CODEC_EN */
+	LP_GPIO_OUT_HIGH,      /* 46: WLAN_DISABLE_L */
+	LP_GPIO_INPUT,         /* 47: RAM_ID2 */
+	LP_GPIO_UNUSED,        /* 48: UNUSED */
+	LP_GPIO_UNUSED,        /* 49: UNUSED */
+	LP_GPIO_UNUSED,        /* 50: UNUSED */
+	LP_GPIO_UNUSED,        /* 51: UNUSED */
+	LP_GPIO_INPUT,         /* 52: SIM_DET */
+	LP_GPIO_PIRQ,          /* 53: TRACKPAD_INT_DX */
+	LP_GPIO_PIRQ,          /* 54: TOUCH_INT_L_DX */
+	LP_GPIO_UNUSED,        /* 55: UNUSED */
+	LP_GPIO_UNUSED,        /* 56: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 57: PP3300_CCD_EN */
+	LP_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	LP_GPIO_OUT_HIGH,      /* 59: LTE_DISABLE_L */
+	LP_GPIO_NATIVE,        /* 60: NATIVE: SML0ALERT */
+	LP_GPIO_UNUSED,        /* 61: UNUSED */
+	LP_GPIO_UNUSED,        /* 62: UNUSED */
+	LP_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	LP_GPIO_UNUSED,        /* 64: UNUSED */
+	LP_GPIO_UNUSED,        /* 65: UNUSED */
+	LP_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 67: UNUSED */
+	LP_GPIO_UNUSED,        /* 68: UNUSED */
+	LP_GPIO_UNUSED,        /* 69: UNUSED */
+	LP_GPIO_UNUSED,        /* 70: UNUSED */
+	LP_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	LP_GPIO_NATIVE,        /* 72: NATIVE: PCH_BATLOW# */
+	LP_GPIO_NATIVE,        /* 73: NATIVE: SMB1ALERT# */
+	LP_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	LP_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	LP_GPIO_UNUSED,        /* 76: UNUSED */
+	LP_GPIO_UNUSED,        /* 77: UNUSED */
+	LP_GPIO_UNUSED,        /* 78: UNUSED */
+	LP_GPIO_UNUSED,        /* 79: UNUSED */
+	LP_GPIO_UNUSED,        /* 80: UNUSED */
+	LP_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	LP_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	LP_GPIO_UNUSED,        /* 83: UNUSED */
+	LP_GPIO_UNUSED,        /* 84: UNUSED */
+	LP_GPIO_UNUSED,        /* 85: UNUSED */
+	LP_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 87: UNUSED */
+	LP_GPIO_UNUSED,        /* 88: UNUSED */
+	LP_GPIO_UNUSED,        /* 89: UNUSED */
+	LP_GPIO_UNUSED,        /* 90: UNUSED */
+	LP_GPIO_UNUSED,        /* 91: UNUSED */
+	LP_GPIO_UNUSED,        /* 92: UNUSED */
+	LP_GPIO_UNUSED,        /* 93: UNUSED */
+	LP_GPIO_UNUSED,        /* 94: UNUSED */
+	LP_GPIO_END
+};
+
+#endif
\ No newline at end of file
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
new file mode 100644
index 0000000000..4bdde31b5d
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <cpu/intel/haswell/haswell.h>
+#include "ec/google/chromeec/ec.h"
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <variant/gpio.h>
+#include "../../variant.h"
+
+const struct rcba_config_instruction rcba_config[] = {
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  PCIE   INTA -> PIRQA
+	 * D29IP_E1P   EHCI   INTA -> PIRQD
+	 * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
+	RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
+	RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+			(INTB << D28IP_P4IP)),
+	RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
+	RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
+	RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
+	RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
+
+	/* Device interrupt route registers */
+	RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
+	RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
+	RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
+	RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
+	RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
+	RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
+	RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
+	RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
+
+	/* Disable unused devices (board specific) */
+	RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+	RCBA_END_CONFIG,
+};
+
+/* Copy SPD data for on-board memory */
+static void copy_spd(struct pei_data *peid)
+{
+	const int gpio_vector[] = {13, 9, 47, -1};
+	int spd_index = get_gpios(gpio_vector);
+	char *spd_file;
+	size_t spd_file_len;
+
+	printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
+	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+						&spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (spd_file_len <
+	    ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+		spd_index = 0;
+	}
+
+	if (spd_file_len < sizeof(peid->spd_data[0]))
+		die("Missing SPD data.");
+
+	/* Index 0-2, are 4GB config with both CH0 and CH1
+	 * Index 3-5, are 2GB config with CH0 only
+	 */
+	switch (spd_index) {
+	case 3: case 4: case 5:
+		peid->dimm_channel1_disabled = 3;
+	}
+
+	memcpy(peid->spd_data[0],
+	       spd_file +
+	       spd_index * sizeof(peid->spd_data[0]),
+	       sizeof(peid->spd_data[0]));
+}
+
+void variant_romstage_entry(unsigned long bist)
+{
+	struct pei_data pei_data = {
+		.pei_version = PEI_VERSION,
+		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
+		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = DEFAULT_PCIEXBAR,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = HPET_ADDR,
+		.rcba = (uintptr_t)DEFAULT_RCBA,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.temp_mmio_base = 0xfed08000,
+		.system_type = 5, /* ULT */
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
+		.ec_present = 1,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.max_ddr3_freq = 1600,
+		.usb_xhci_on_resume = 1,
+		.usb2_ports = {
+			/* Length, Enable, OCn#, Location */
+			{ 0x0040, 1, 0,               /* P0: Port A, CN10 */
+			  USB_PORT_BACK_PANEL },
+			{ 0x0040, 1, 2,               /* P1: Port B, CN11  */
+			  USB_PORT_BACK_PANEL },
+			{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+			  USB_PORT_INTERNAL },
+			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+			  USB_PORT_MINI_PCIE },
+			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
+			  USB_PORT_INTERNAL },
+			{ 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */
+			  USB_PORT_SKIP },
+			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+			  USB_PORT_INTERNAL },
+			{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+			  USB_PORT_SKIP  },
+		},
+		.usb3_ports = {
+			/* Enable, OCn# */
+			{ 1, 0               }, /* P1; Port A, CN10 */
+			{ 1, 2               }, /* P2; Port B, CN11  */
+			{ 0, USB_OC_PIN_SKIP }, /* P3; */
+			{ 0, USB_OC_PIN_SKIP }, /* P4; */
+		},
+	};
+
+	struct romstage_params romstage_params = {
+		.pei_data = &pei_data,
+		.gpio_map = &mainboard_gpio_map,
+		.rcba_config = &rcba_config[0],
+		.bist = bist,
+		.copy_spd = copy_spd,
+	};
+
+	/* Call into the real romstage main with this board's attributes. */
+	romstage_common(&romstage_params);
+}
diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex
new file mode 100644
index 0000000000..7b0932743d
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6AFR6A-PBA
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
+48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex
new file mode 100644
index 0000000000..cbe9e4fbfe
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex
@@ -0,0 +1,17 @@
+# Micron 4KTF25664HZ-1G6E1
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
+34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
+31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex
new file mode 100644
index 0000000000..fb529d01db
--- /dev/null
+++ b/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646B-HYXX
+92 11 0B 03 04 19 02 02 03 11 01 08 0C 00 3E 00
+69 78 69 3C 69 11 20 89 20 08 3C 3C 01 68 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 2A E3
+4D 34 37 31 42 35 36 37 34 42 48 30 2D 43 48 39
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
\ No newline at end of file