diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 01:43:04 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:15:54 +0000 |
commit | 8d3bc498760fdf98713f1d977a79268d2fb1288c (patch) | |
tree | 759a00420ab4f9036c3040f08afdbfbfda14473b /src/mainboard/google/slippy/variants/wolf/romstage.c | |
parent | e12de372d7c22ae6414ad393a82214f6b8028d7e (diff) |
mb/google/slippy: Factor out common romstage settings
There's no need to repeat the same values over four variants.
Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/google/slippy/variants/wolf/romstage.c')
-rw-r--r-- | src/mainboard/google/slippy/variants/wolf/romstage.c | 128 |
1 files changed, 30 insertions, 98 deletions
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7ebb7aa61c..fd8e63275c 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -13,46 +13,6 @@ #include <variant/gpio.h> #include "../../variant.h" -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - - RCBA_END_CONFIG, -}; - /* Copy SPD data for on-board memory */ static void copy_spd(struct pei_data *peid) { @@ -91,67 +51,39 @@ static void copy_spd(struct pei_data *peid) } } -void variant_romstage_entry(void) +void variant_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0040, 1, 0, /* P0: Port A, CN10 */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, 2, /* P1: Port B, CN11 */ - USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ - USB_PORT_INTERNAL }, - { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_INTERNAL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ - USB_PORT_SKIP }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN11 */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }, + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, }; - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .copy_spd = copy_spd, + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ }; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); + + rp->gpio_map = &mainboard_gpio_map; + rp->copy_spd = copy_spd; } |