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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-30 02:11:24 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-31 10:34:42 +0000 |
| commit | 61ba3ac92e832259acd831ab6fab2946f57c7035 (patch) | |
| tree | b6351d96549e9d6bace8cde0c89dbdbf2e9dd744 /src/mainboard/google/slippy/variants/wolf/overridetree.cb | |
| parent | 98f609aad4b6d6b6a09efaa011a1f02116935acd (diff) | |
mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/slippy/variants/wolf/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/slippy/variants/wolf/overridetree.cb | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb new file mode 100644 index 0000000000..5ccca1d821 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -0,0 +1,25 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end + end +end |