diff options
| author | Furquan Shaikh <furquan@google.com> | 2013-08-06 13:48:12 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-13 19:32:56 +0200 |
| commit | c1c6dcf0f3bb332cf493969082414df16c025a32 (patch) | |
| tree | a3c25ee44e4e2aa52b47d92d0ba5706f553ef67a /src/mainboard/google/slippy/gma.c | |
| parent | 77f48cdeade7fc296fb5c973b6b0191ac5bd8c35 (diff) | |
Falco: Patch to enable correct port clock selection for dp
This is required only for haswell since the register configs have changed.
Also, created mainboard specific header file
Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945
Signed-off-by: Furquan Shaikh <furquan@google.com>
Conflicts:
src/mainboard/google/slippy/gma.c
src/mainboard/google/slippy/i915io.c
Conflicts:
src/mainboard/google/slippy/gma.c
Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5
Reviewed-on: https://gerrit.chromium.org/gerrit/66853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6602
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/slippy/gma.c')
| -rw-r--r-- | src/mainboard/google/slippy/gma.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index 7c95e40667..839fa4dc2a 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include <drivers/intel/gma/i915.h> +#include "mainboard.h" /* * Here is the rough outline of how we bring up the display: @@ -228,7 +229,6 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw) } } -void mainboard_train_link(struct intel_dp *intel_dp); void mainboard_train_link(struct intel_dp *intel_dp) { u8 read_val; @@ -281,6 +281,29 @@ static void test_gfx(struct intel_dp *dp) static void test_gfx(struct intel_dp *dp) {} #endif + +void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) +{ + u32 ddi_pll_sel = 0; + + switch (intel_dp->link_bw) { + case DP_LINK_BW_1_62: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; + break; + case DP_LINK_BW_2_7: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; + break; + case DP_LINK_BW_5_4: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; + break; + default: + printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); + return; + } + + gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); +} + int i915lightup(unsigned int pphysbase, unsigned int pmmio, unsigned int pgfx, unsigned int init_fb) { |