diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-04-29 15:10:31 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-11-24 06:15:12 +0100 |
| commit | cf72d91613eef7a2ff7ed2145cd8baefff35eb16 (patch) | |
| tree | 6d52eb31d1fe22b07aeed9303fa52c197982951a /src/mainboard/google/slippy/devicetree.cb | |
| parent | 7797ffa1bebfefde0076383a12f620897e5ef81a (diff) | |
slippy: Initial mainboard commit
Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49531
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4147
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/google/slippy/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb new file mode 100644 index 0000000000..8cf387fff8 --- /dev/null +++ b/src/mainboard/google/slippy/devicetree.cb @@ -0,0 +1,89 @@ +chip northbridge/intel/haswell + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/haswell + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S) + register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end |