diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2023-05-19 09:57:48 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-05-23 02:03:52 +0000 |
| commit | a398b311084c60b3ed31fdda93217780bc38a497 (patch) | |
| tree | b071e2d8ce3e8d4344b78c09fd0ffd74369508dc /src/mainboard/google/skyrim | |
| parent | d6b4db159b60089c3d6e9aad993804ea319047e2 (diff) | |
mb/google/skyrim/var/markarth: Update DPTC and STT settings
According to Thermal table 0518, adjust DPTC and STT settings.
BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/skyrim')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/markarth/overridetree.cb | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb index 3939d657ee..bdfd3fd457 100644 --- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb @@ -3,8 +3,21 @@ chip soc/amd/mendocino # Set Package Power Parameters - # Remove the sustained_power_limit_mW when STT is enabled - register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "92" + + # STT settings + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_error_coeff" = "0x0038" + register "stt_error_rate_coefficient" = "0x0ed9" + register "stt_min_limit" = "15000" + register "stt_skin_temp_apu" = "0x2700" + + # STT default mode + register "stt_m1" = "0x036b" + register "stt_m2" = "0x0022" + register "stt_c_apu" = "0xffc1" + register "stt_alpha_apu" = "0x199a" # set usb3 port force to gen1 register "usb3_port_force_gen1" = "{ |