diff options
| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2023-02-17 15:09:06 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 02:31:11 +0000 |
| commit | 29863f6cf295661722533fd60b5c24257769f8b9 (patch) | |
| tree | 039625d5b42b86f1f4061269f91627a9226d6dfa /src/mainboard/google/skyrim/variants | |
| parent | 2809507ca7d4a428ee64b43a37dfe990c9966f12 (diff) | |
mb/google/skyrim/var/frostflow: Update DPTC and STT settings
According to thermal_table_0215, adjust DPTC and STT settings.
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/skyrim/variants')
| -rw-r--r-- | src/mainboard/google/skyrim/variants/frostflow/overridetree.cb | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index b34e2e35a9..86b1c94193 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -147,4 +147,27 @@ chip soc/amd/mendocino end end # UART1 + # Set Package Power Parameters + register "thermctl_limit_degreeC" = "90" + + # STT settings + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0x2666" + register "stt_min_limit" = "15000" + register "stt_skin_temp_apu" = "0x3000" + + # STT default mode + register "stt_m1" = "0xfed2" + register "stt_m2" = "0x5f9" + register "stt_c_apu" = "0xfbf8" + register "stt_alpha_apu" = "0x4ccd" + + # STT tablet mode + register "stt_m1_tablet" = "0x208" + register "stt_m2_tablet" = "0x1f5" + register "stt_c_apu_tablet" = "0xa2" + register "stt_alpha_apu_tablet" = "0x199a" + end # chip soc/amd/mendocino |