diff options
| author | Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com> | 2019-10-31 15:45:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-27 13:50:14 +0000 |
| commit | d367503147125210fbc09fa43628d233840f2c65 (patch) | |
| tree | 35dfbcf5eee97f09d7f51b37bd2e0be351effc8a /src/mainboard/google/sarien | |
| parent | b0f15f0f86b13257fdbf3ce2c2c651c40116994c (diff) | |
soc/intel/cannonlake: Disable USB2 PHY Power gating
Workaround to disable USB2 PHY power gating to fix issue seen when
Apple 87W USB-C charger is connected in S0ix state on WHL platforms
(based on Intel's recommendation). Issue is seen on CML platforms also.
So, disable power gating for Drallion too.
Add devicetree entry to set the flag to disable USB2 PHY power gating
for different CNL PCH based platforms
BUG=b:133775942
TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if
the system wakes up after that
Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com>
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4af8ca25ca..6bc3df11af 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index cd216e593b..b2aa8d5e8d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,8 @@ chip soc/intel/cannonlake register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" |