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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-15 10:52:42 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-18 16:04:31 +0000 |
| commit | 6d391e649f8a32613d489e513eb00c05d07a7147 (patch) | |
| tree | fff5b113ac272ebc9adfc3df40c168aad786f0f0 /src/mainboard/google/sarien | |
| parent | ff75c21e6d6c84d4d78529afc1b145104631eaa9 (diff) | |
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's
dptf.asl file, and I forgot to update the devicetree with TSR3 as well.
Also missed a swap in the passive policies of TSR0 and TSR1. This patch
fixes those.
BUG=b:149722146
TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/sarien')
0 files changed, 0 insertions, 0 deletions