diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-06 17:12:40 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-11 08:59:02 +0000 |
| commit | 2d92b1a3b1f2f42f36e035163b4658d440a082e1 (patch) | |
| tree | f21d9640b6ecef1db9e450b298191244279a6eca /src/mainboard/google/sarien | |
| parent | 4cdb2b9b75fe2cf722b0409652a0d660b58fecfd (diff) | |
mb/google/sarien: Disable PCH Gigabit LAN
There's no LAN connection on Arcada board, so disable PCH GBE.
BUG=N/A
Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fccec9f3b6..924f51d17f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -78,11 +78,6 @@ chip soc/intel/cannonlake }, }" - # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 10 for M.2 2230 WLAN register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[2]" = "9" @@ -250,6 +245,6 @@ chip soc/intel/cannonlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end |