diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2020-07-21 18:48:42 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-23 17:06:14 +0000 |
| commit | e00db59c7c14c5914eab34fbf0c4b929cb50d2eb (patch) | |
| tree | 66cd92dd9283b164a75e6a35f193cdaddfdc74d8 /src/mainboard/google/sarien | |
| parent | 311ddbd193dd0702b8f506ace32facf6402b6e8e (diff) | |
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972
BRANCH=sarien
TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a84e73a826..7e4da3fff8 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -382,6 +382,10 @@ chip soc/intel/cannonlake device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 |