diff options
| author | Nico Huber <nico.huber@secunet.com> | 2019-10-02 16:02:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-08-23 09:57:02 +0000 |
| commit | 119ace0908b66b718c4b581423309648b10e4bf7 (patch) | |
| tree | b9ed4510a9081065c35af99a06446a74b3db82c1 /src/mainboard/google/sarien | |
| parent | 2b9035ed6e51fe835b85dd626e655e1d3901e7ea (diff) | |
soc/intel/cnl: Configure FSP option PcieRpSlotImplemented
Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.
Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/sarien')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 14 |
2 files changed, 16 insertions, 4 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index bacc6dceb7..760e35146e 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -377,8 +377,11 @@ chip soc/intel/cannonlake device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[9]" = "1" end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.2 on # PCI Express Port 11 + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on chip drivers/generic/bayhub @@ -386,6 +389,7 @@ chip soc/intel/cannonlake device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e79a8a5aeb..78f024cbf4 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -385,22 +385,29 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 (USB) + device pci 1c.0 on # PCI Express Port 1 (USB) + register "PcieRpSlotImplemented[0]" = "1" + end device pci 1c.1 off end # PCI Express Port 2 (USB) device pci 1c.2 off end # PCI Express Port 3 (USB) device pci 1c.3 off end # PCI Express Port 4 (USB) device pci 1c.4 off end # PCI Express Port 5 (USB) device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on end # PCI Express Port 8 + device pci 1c.7 on # PCI Express Port 8 + register "PcieRpSlotImplemented[7]" = "1" + end device pci 1d.0 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.1 on # PCI Express Port 10 + register "PcieRpSlotImplemented[9]" = "1" + end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on @@ -409,6 +416,7 @@ chip soc/intel/cannonlake device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 |