diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2019-03-29 17:08:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-03 08:46:25 +0000 |
| commit | 0a4dcee75f03a0154f7a418d24ec643a020ea401 (patch) | |
| tree | ce1d2e310d13a17ff2e4c8e37104434d0b4fd859 /src/mainboard/google/sarien/variants | |
| parent | 622a28d22b917dec29d8b75aab8cdf55300a7e4c (diff) | |
mb/google/sarien/variants/sarien: Update thermal configuration for DPTF
Follow thermal table for second tunning.
BUG=b:129509918
TEST=Built and tested on sarien system
Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/sarien/variants')
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl | 18 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 72dea1ee14..caae79f036 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,7 +42,7 @@ chip soc/intel/cannonlake register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" - register "tdp_pl1_override" = "25" + register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" # Enable eDP device diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index be052f8c37..0cdbcd1400 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 99 #define DPTF_CPU_CRITICAL 105 /* Skin Sensor for CPU VR temperature monitor */ @@ -25,7 +25,7 @@ /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 56 +#define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_CRITICAL 100 /* M.2 Sensor for Ambient temperature monitor */ @@ -39,16 +39,16 @@ Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 5000, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 200, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 2000, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 250, 10, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 250, 10, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,15 +56,15 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 25000, /* PowerLimitMaximum */ + 5000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 10000, /* TimeWindowMinimum */ 10000, /* TimeWindowMaximum */ 100 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 3000, /* PowerLimitMinimum */ + 5000, /* PowerLimitMinimum */ 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMaximum */ |