diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-20 21:34:40 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-21 22:27:08 +0000 |
| commit | bb3d01a24959c507fa8efb28d654b1e69cc660cc (patch) | |
| tree | a99a880810bbac6f57f245096e58af9a70c49d51 /src/mainboard/google/sarien/variants | |
| parent | 7ec8d4b8f05434c6705f79bd00863a6dd0b6c836 (diff) | |
mb/google/sarien: Disable pcie interface for wwan
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the
usgae of Sarien choose to only use USB interface but not over pci
express, so totally disable pci express root port 12.
BUG=b:1246720
TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10
cyles can still device can be listed under lsusb.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d
Reviewed-on: https://review.coreboot.org/c/30350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/sarien/variants')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 7 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 7 |
2 files changed, 2 insertions, 12 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a8bb34233a..52840de860 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -86,11 +86,6 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" - # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[3]" = "11" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" @@ -240,7 +235,7 @@ chip soc/intel/cannonlake device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c24cd028e1..47abadc5d9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -95,11 +95,6 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" - # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[0]" = "11" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" @@ -259,7 +254,7 @@ chip soc/intel/cannonlake device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 |