diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-11-20 17:33:12 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-04 22:49:25 +0000 |
| commit | 833a3a879d9af4c793233dd537f5fa9da5b3c110 (patch) | |
| tree | cf0108417fc0915386debca95cc63dfdfb894917 /src/mainboard/google/sarien/variants/arcada/devicetree.cb | |
| parent | bfb001d1a0b953fd832fce6bb13c02657ab1139f (diff) | |
mb/google/sarien: Enable DPTF
Enable DPTF support for sarien/arcada boards. This is currently
using placeholder values that are identical that will be updated
after thermal tuning is done.
Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/sarien/variants/arcada/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee1cca09f0..4bd2d90c94 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -30,6 +30,7 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" + register "dptf_enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C |