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authorYidi Lin <yidilin@chromium.org>2023-08-07 14:29:48 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-08-11 17:54:27 +0000
commitce1ef69850b56cc74f94ffe57ca9472a3fc92124 (patch)
treeb3d0242d6aab4e122c098bef854b043316561094 /src/mainboard/google/sarien/ec.c
parent27172065fbdfc2e33848f98b29d8211fff045703 (diff)
mb/google/geralt: Move I2C and SPI initialization to verstage
After enabling VBOOT_CBFS_INTEGRATION, bootblock exceeds allocated size (60K) by 3.5K. Since TPM and EC won't be accessed in bootblock, we move I2C and SPI initializaion to verstage to reduce bootblock size. The GSC interrupt pin configuration is also moved to verstage to save more spaces for bootblock. The size of bootblock.raw.bin is reduced from 64,040 bytes to 60,808 bytes. BUG=b:294643742 TEST=boot to kernel Change-Id: I5f6855d5a1a0fce6e739d44652c88e406f6f7b89 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/sarien/ec.c')
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