aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/sarien/Kconfig
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@google.com>2018-10-31 10:38:16 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-11-02 16:07:13 +0000
commit558602ff4043082f3e0fc91cbf4905302853a94c (patch)
treeb559fe485596ac9b9bc7e75148242bf84988e9ff /src/mainboard/google/sarien/Kconfig
parentdb48f7ea48205f69f0c1dd86d71ba0d7fe022d4a (diff)
mb/google/sarien: Add new mainboard
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/sarien/Kconfig')
-rw-r--r--src/mainboard/google/sarien/Kconfig89
1 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
new file mode 100644
index 0000000000..4bf5191270
--- /dev/null
+++ b/src/mainboard/google/sarien/Kconfig
@@ -0,0 +1,89 @@
+
+config BOARD_GOOGLE_BASEBOARD_SARIEN
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_SPI_ACPI
+ select DRIVERS_PS2_KEYBOARD
+ select GENERIC_SPD_BIN
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select SOC_INTEL_COFFEELAKE
+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+ select TPM2
+
+if BOARD_GOOGLE_BASEBOARD_SARIEN
+
+config CHROMEOS
+ bool
+ default y
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+
+config DEVICETREE
+ string
+ default "variants/sarien/devicetree.cb" if BOARD_GOOGLE_SARIEN
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x4
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x50
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 82 # GPE0_DW2_18 (GPP_D18)
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN
+
+config MAINBOARD_DIR
+ string
+ default "google/sarien"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Sarien" if BOARD_GOOGLE_SARIEN
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Sarien" if BOARD_GOOGLE_SARIEN
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config MAX_CPUS
+ int
+ default 8
+
+config VARIANT_DIR
+ string
+ default "sarien" if BOARD_GOOGLE_SARIEN
+
+config VBOOT
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_BASEBOARD_SARIEN