diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2014-06-18 14:03:08 +0800 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-09 07:45:32 +0100 |
commit | c25318938fd9b86969057f3b4e741b949624ec41 (patch) | |
tree | 7f0cf74c29f1414ff245dba3b6d3f1092b73345c /src/mainboard/google/samus/spd/spd.c | |
parent | bb0d5ef97a10bada5310ec7fc4faf53a15e98e71 (diff) |
samus: Updates from P2 build
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/spd/spd.c')
-rw-r--r-- | src/mainboard/google/samus/spd/spd.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 0409302fb0..00e694e9d2 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -24,6 +24,8 @@ #include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/romstage.h> +#include <ec/google/chromeec/ec.h> +#include <mainboard/google/samus/ec.h> #include <mainboard/google/samus/gpio.h> #include <mainboard/google/samus/spd/spd.h> @@ -80,25 +82,33 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { + int spd_bits[4] = { + SPD_GPIO_BIT0, + SPD_GPIO_BIT1, + SPD_GPIO_BIT2, + SPD_GPIO_BIT3 + }; int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file; - spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); - spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); - spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); - spd_gpio[3] = get_gpio(SPD_GPIO_BIT3); + /* Proto2B boards use a different GPIO for SPD index bit 3 */ + if (google_chromeec_get_board_version() <= SAMUS_EC_BOARD_PROTO2_A) + spd_bits[3] = SPD_GPIO_BIT3_OLD; + + spd_gpio[0] = get_gpio(spd_bits[0]); + spd_gpio[1] = get_gpio(spd_bits[1]); + spd_gpio[2] = get_gpio(spd_bits[2]); + spd_gpio[3] = get_gpio(spd_bits[3]); spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | (spd_gpio[1] << 1) | spd_gpio[0]; printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " "GPIO%d=%d GPIO%d=%d)\n", spd_index, - SPD_GPIO_BIT3, spd_gpio[3], - SPD_GPIO_BIT2, spd_gpio[2], - SPD_GPIO_BIT1, spd_gpio[1], - SPD_GPIO_BIT0, spd_gpio[0]); + spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], + spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); if (!spd_file) @@ -120,5 +130,9 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) memcpy(pei_data->spd_data[1][0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + mainboard_print_spd_info(pei_data->spd_data[0][0]); } |