Add/Combine Broadwell Chromebooks using variant board scheme

Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 67 deletions

diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
deleted file mode 100644
index 2306a2942c..0000000000
--- a/src/mainboard/google/samus/romstage.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-#include <ec/google/chromeec/ec.h>
-#include <soc/cpu.h>
-#include <soc/gpio.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <mainboard/google/samus/spd/spd.h>
-#include <mainboard/google/samus/gpio.h>
-#include <ec/google/chromeec/ec.h>
-#include "board_version.h"
-
-void mainboard_romstage_entry(struct romstage_params *rp)
-{
-	struct pei_data pei_data;
-
-	post_code(0x31);
-
-	if (rp->power_state->prev_sleep_state != ACPI_S3)
-		google_chromeec_kbbacklight(100);
-
-	printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
-
-	/* Ensure the EC and PD are in the right mode for recovery */
-	google_chromeec_early_init();
-
-	/* Initialize GPIOs */
-	init_gpios(mainboard_gpio_config);
-
-	/* Fill out PEI DATA */
-	memset(&pei_data, 0, sizeof(pei_data));
-	mainboard_fill_pei_data(&pei_data);
-	mainboard_fill_spd_data(&pei_data);
-	rp->pei_data = &pei_data;
-
-	/* Initalize memory */
-	romstage_common(rp);
-
-	/* Bring SSD out of reset */
-	set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH);
-
-	/*
-	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
-	 * to prevent possible brownout.
-	 */
-	set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH);
-}