diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-05-22 08:25:36 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:03:54 +0100 |
| commit | 25c6f75bb29fceba7a30d170f2401241fc3428ed (patch) | |
| tree | f05601525d0177b05a915a7243485f4967c28c22 /src/mainboard/google/samus/romstage.c | |
| parent | fe8b788a12b225ae45ecb26625cfd2588d193ff3 (diff) | |
samus: Update for board revision 1.9
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/romstage.c')
| -rw-r--r-- | src/mainboard/google/samus/romstage.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9af4ffbc5c..959428732f 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,12 +22,13 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> #include <mainboard/google/samus/spd/spd.h> -#include "gpio.h" +#include <mainboard/google/samus/gpio.h> void mainboard_romstage_entry(struct romstage_params *rp) { @@ -35,6 +36,9 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); + printk(BIOS_INFO, "MLB: board version %d\n", + google_chromeec_get_board_version()); + /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); @@ -47,6 +51,16 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; + /* + * http://crosbug.com/p/29117 + * Limit Broadwell SKU to 1333MHz and disable channel 1 + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.max_ddr3_freq = 1333; + pei_data.dimm_channel1_disabled = 3; + memset(pei_data.spd_data[1][0], 0, SPD_LEN); + } + romstage_common(rp); /* |