diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-06-18 14:03:08 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-09 07:45:32 +0100 |
| commit | c25318938fd9b86969057f3b4e741b949624ec41 (patch) | |
| tree | 7f0cf74c29f1414ff245dba3b6d3f1092b73345c /src/mainboard/google/samus/romstage.c | |
| parent | bb0d5ef97a10bada5310ec7fc4faf53a15e98e71 (diff) | |
samus: Updates from P2 build
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/romstage.c')
| -rw-r--r-- | src/mainboard/google/samus/romstage.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 959428732f..c9e13e1dfb 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -22,8 +22,7 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <broadwell/cpu.h> -//#include <broadwell/gpio.h> +#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> @@ -51,16 +50,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; - /* - * http://crosbug.com/p/29117 - * Limit Broadwell SKU to 1333MHz and disable channel 1 - */ - if (cpu_family_model() == BROADWELL_FAMILY_ULT) { - pei_data.max_ddr3_freq = 1333; - pei_data.dimm_channel1_disabled = 3; - memset(pei_data.spd_data[1][0], 0, SPD_LEN); - } - romstage_common(rp); /* |