diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-09-29 08:35:29 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:50 +0200 |
| commit | 1247b8734d20f623a9d6fc7ee62e77920b096d37 (patch) | |
| tree | a633a64b77f546260bc9f8dc962950fba2120b1a /src/mainboard/google/samus/romstage.c | |
| parent | d840118ef59bdd0f89c989c0c1d43d32e13ce9d1 (diff) | |
samus: Fix and clean up GPIOs and EC info/events
- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board
BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa
Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220321
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/samus/romstage.c')
| -rw-r--r-- | src/mainboard/google/samus/romstage.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index ca43b81bf6..39a23f0b6a 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -56,13 +56,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; - /* - * Disable use of PEI saved data to work around memory issues. - */ - if (cpu_family_model() == BROADWELL_FAMILY_ULT) { - pei_data.disable_cmd_pwr = 1; - } - /* Initalize memory */ romstage_common(rp); |