samus: Update for board revision 1.9

- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU

BUG=chrome-os-partner:28234
TEST=Boot on P1.9

Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 70 deletions

diff --git a/src/mainboard/google/samus/onboard.h b/src/mainboard/google/samus/onboard.h
deleted file mode 100644
index d47d3c99ee..0000000000
--- a/src/mainboard/google/samus/onboard.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef ONBOARD_H
-#define ONBOARD_H
-
-#define BOARD_PIRQ_INTERRUPT		0
-#define BOARD_GPIO_INTERRUPT		1
-#define BOARD_GPIO_OFFSET		162
-#define GPIO_INTERRUPT(x)		(BOARD_GPIO_OFFSET + (x))
-
-#define BOARD_TRACKPAD_NAME		"trackpad"
-#define BOARD_TRACKPAD_IRQ		27	/* PIRQL */
-#define BOARD_TRACKPAD_IRQ_TYPE		BOARD_PIRQ_INTERRUPT
-#define BOARD_TRACKPAD_WAKE_GPIO	13	/* GPIO13 */
-#define BOARD_TRACKPAD_I2C_BUS		1	/* I2C0 */
-#define BOARD_TRACKPAD_I2C_ADDR		0x4b
-
-#define BOARD_TOUCHSCREEN_NAME		"touchscreen"
-#define BOARD_TOUCHSCREEN_IRQ		28	/* PIRQM */
-#define BOARD_TOUCHSCREEN_IRQ_TYPE	BOARD_PIRQ_INTERRUPT
-#define BOARD_TOUCHSCREEN_WAKE_GPIO	14	/* GPIO14 */
-#define BOARD_TOUCHSCREEN_I2C_BUS	2	/* I2C1 */
-#define BOARD_TOUCHSCREEN_I2C_ADDR	0x4b
-
-#define BOARD_CODEC_NAME		"codec"
-#define BOARD_CODEC_IRQ			30	/* PIRQO */
-#define BOARD_CODEC_IRQ_TYPE		BOARD_PIRQ_INTERRUPT
-#define BOARD_CODEC_WAKE_GPIO		46	/* GPIO46 */
-#define BOARD_CODEC_I2C_BUS		1	/* I2C0 */
-#define BOARD_CODEC_I2C_ADDR		0x1a
-
-#define BOARD_NFC_NAME			"nfc"
-#define BOARD_NFC_IRQ			GPIO_INTERRUPT(9)
-#define BOARD_NFC_IRQ_TYPE		BOARD_GPIO_INTERRUPT
-#define BOARD_NFC_WAKE_GPIO		9	/* GPIO9 */
-#define BOARD_NFC_I2C_BUS		1	/* I2C0 */
-#define BOARD_NFC_I2C_ADDR		0x28
-
-#define BOARD_ACCEL_NAME		"accel"
-#define BOARD_ACCEL_IRQ			29	/* PIRQN */
-#define BOARD_ACCEL_IRQ_TYPE		BOARD_PIRQ_INTERRUPT
-#define BOARD_ACCEL_WAKE_GPIO		45	/* GPIO45 */
-#define BOARD_ACCEL_I2C_BUS		2	/* I2C1 */
-#define BOARD_ACCEL_I2C_ADDR		0x0e
-
-#define BOARD_ACCEL_GYRO_NAME		"accel_gyro"
-#define BOARD_ACCEL_GYRO_IRQ		31	/* PIRQP */
-#define BOARD_ACCEL_GYRO_IRQ_TYPE	BOARD_PIRQ_INTERRUPT
-#define BOARD_ACCEL_GYRO_WAKE_GPIO	47	/* GPIO47 */
-#define BOARD_ACCEL_GYRO_I2C_BUS	2	/* I2C1 */
-#define BOARD_ACCEL_GYRO_I2C_ADDR	0x6b
-
-#endif