diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-10-02 16:10:54 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-08-29 06:48:01 +0200 |
| commit | ddc3e42c2267fe175dcc28e38f53f0adecf1aa4e (patch) | |
| tree | 66326a007407b0efcdcef7121a64f6a0263d2d57 /src/mainboard/google/samus/gpio.h | |
| parent | ca436cb247a78b234feb7975575883bdcbabc348 (diff) | |
samus: Add coreboot board
Add the coreboot board files for samus
- Based on Bolt
- GPIO setup based on 0.91 schematic
- Support both memory types
- No HDA verb table for this platform
- Some GPIO interrupts are shared and need to be passed to OS
Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171694
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6775
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/samus/gpio.h')
| -rw-r--r-- | src/mainboard/google/samus/gpio.h | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h new file mode 100644 index 0000000000..353d32a1a9 --- /dev/null +++ b/src/mainboard/google/samus/gpio.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SAMUS_GPIO_H +#define SAMUS_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ + LP_GPIO_UNUSED, /* 9: UNUSED */ + LP_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_UNUSED, /* 12: UNUSED */ + LP_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */ + LP_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_INPUT, /* 16: PCH_WP */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_OUT_HIGH, /* 23: PP3300_AUTOBAHN_EN */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT, /* 25: EC_IN_RW */ + LP_GPIO_OUT_HIGH, /* 26: NFC_EN */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 29: NFC_INT (GPIO IRQ) */ + LP_GPIO_NATIVE, /* 29: NATIVE: WLAN_OFF_L */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */ + LP_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ + LP_GPIO_IRQ_EDGE, /* 42: CODEC_INT_L (GPIO IRQ) */ + LP_GPIO_IRQ_EDGE, /* 43: ACCEL_INT (GPIO IRQ) */ + LP_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */ + LP_GPIO_OUT_HIGH, /* 45: PP1800_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_OUT_HIGH, /* 49: HDMI_CEC */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_UNUSED, /* 51: UNUSED */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_UNUSED, /* 53: UNUSED */ + LP_GPIO_UNUSED, /* 54: UNUSED */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */ + LP_GPIO_UNUSED, /* 58: UNUSED */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_UNUSED, /* 60: UNUSED */ + LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ + LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_OUT_HIGH, /* 64: NFS_FW_UPDATE */ + LP_GPIO_OUT_HIGH, /* 65: MINIDP_PWR_FLT_L */ + LP_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */ + LP_GPIO_INPUT, /* 67: RAM_ID0 */ + LP_GPIO_INPUT, /* 68: RAM_ID1 */ + LP_GPIO_INPUT, /* 69: RAM_ID2 */ + LP_GPIO_OUT_HIGH, /* 70: LTE_POWER_ON */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_UNUSED, /* 72: UNUSED */ + LP_GPIO_UNUSED, /* 73: UNUSED */ + LP_GPIO_UNUSED, /* 74: UNUSED */ + LP_GPIO_UNUSED, /* 75: UNUSED */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_UNUSED, /* 81: UNUSED */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */ + LP_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */ + LP_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */ + LP_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */ + LP_GPIO_END +}; + +#endif |