diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-07-14 11:50:09 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-05 17:32:08 +0100 |
| commit | 9c8cfc5c25876991751ff4e533a0c421203139c8 (patch) | |
| tree | d838fe039d49bd523c00bd728a5acf9eb3fcf9e0 /src/mainboard/google/rush_ryu | |
| parent | f13c567c9713538789ec3ef3f478e1c52816d959 (diff) | |
coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.
BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.
Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207815
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-on: http://review.coreboot.org/8592
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/rush_ryu')
0 files changed, 0 insertions, 0 deletions