tegra132: use pre-existing reset API

coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().

For the existing tegra132 boards remove the unnecessary files
from the build.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.

Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 6 insertions, 30 deletions

diff --git a/src/mainboard/google/rush_ryu/Makefile.inc b/src/mainboard/google/rush_ryu/Makefile.inc
index 9faba250d4..4f50c6be5c 100644
--- a/src/mainboard/google/rush_ryu/Makefile.inc
+++ b/src/mainboard/google/rush_ryu/Makefile.inc
@@ -32,8 +32,10 @@ bootblock-y += pmic.c
 bootblock-y += reset.c
 
 romstage-y += reset.c
+romstage-y += reset.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
 
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
+ramstage-y += reset.c
diff --git a/src/mainboard/google/rush_ryu/reset.c b/src/mainboard/google/rush_ryu/reset.c
index 381634078b..f3057cac90 100644
--- a/src/mainboard/google/rush_ryu/reset.c
+++ b/src/mainboard/google/rush_ryu/reset.c
@@ -18,12 +18,11 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 #include <soc/nvidia/tegra132/gpio.h>
 
-#include "reset.h"
-
-void cpu_reset(void)
+void hard_reset(void)
 {
-        gpio_output(GPIO(I5), 0);
-        while(1);
+	gpio_output(GPIO(I5), 0);
+	while(1);
 }
diff --git a/src/mainboard/google/rush_ryu/reset.h b/src/mainboard/google/rush_ryu/reset.h
deleted file mode 100644
index be723ce316..0000000000
--- a/src/mainboard/google/rush_ryu/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
-#define __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__
-
-void cpu_reset(void);
-
-#endif /* __MAINBOARD_GOOGLE_RUSH_BOOTBLOCK_H__ */