diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-07-14 19:09:23 -0500 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-05 17:32:50 +0100 |
commit | 072e0cc899aa11ca55fecd9e8a384a045975f735 (patch) | |
tree | 0e296f7fa4e36f6973568735de07e4d17d2a7ab2 /src/mainboard/google/rush_ryu/bct/spi.cfg | |
parent | 5f66b5246443e4387a4147745666dc091556ff07 (diff) |
rush_ryu: Add new mainboard
This is a clone of rush for the time being. All the incompatible
bits can be moved later. Additional patches to follow.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board
Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207838
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab
Reviewed-on: http://review.coreboot.org/8594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/mainboard/google/rush_ryu/bct/spi.cfg')
-rw-r--r-- | src/mainboard/google/rush_ryu/bct/spi.cfg | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/rush_ryu/bct/spi.cfg b/src/mainboard/google/rush_ryu/bct/spi.cfg new file mode 100644 index 0000000000..a5ded0bd68 --- /dev/null +++ b/src/mainboard/google/rush_ryu/bct/spi.cfg @@ -0,0 +1,31 @@ +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00130001; +BlockSize = 32768; +PageSize = 2048; +PartitionSize = 4194304; + +DevType[0] = NvBootDevType_Spi; +DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; + +DevType[1] = NvBootDevType_Spi; +DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[1].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0; + +DevType[2] = NvBootDevType_Spi; +DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[2].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0; + +DevType[3] = NvBootDevType_Spi; +DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; |