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authorMatt DeVillier <matt.devillier@gmail.com>2015-12-25 01:36:40 -0600
committerMartin Roth <martinroth@google.com>2016-06-16 01:43:42 +0200
commitf09d39db4ed3be7a0d4e452e3564c34e064a437a (patch)
tree889dcf8c880e8067cc5555cf3e36f6edf9eafe2e /src/mainboard/google/rikku/acpi/superio.asl
parent1f40ae2d746ec9a85770538a2e21620934331bd9 (diff)
google/rikku: Upstream Acer Chromebox CXI2
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to upstream, using google/guado as a baseline. original source: branch firmware-rikku-6301.110.B commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F] TEST=built and booted Linux on rikku with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.bin) external reference code (refcode.elf) Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12802 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/rikku/acpi/superio.asl')
-rw-r--r--src/mainboard/google/rikku/acpi/superio.asl32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/rikku/acpi/superio.asl b/src/mainboard/google/rikku/acpi/superio.asl
new file mode 100644
index 0000000000..a65b3f5ef0
--- /dev/null
+++ b/src/mainboard/google/rikku/acpi/superio.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
+
+#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard
+#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse
+#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
+#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
+
+#include "superio/ite/it8772f/acpi/superio.asl"
+