diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-01-20 22:04:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-24 05:44:10 +0000 |
| commit | cbca81c5946384843197c08401c4266f45fef4a2 (patch) | |
| tree | edf65c4a7a62c0075c5950ff16bfe05f87f43c78 /src/mainboard/google/rex | |
| parent | 289f9a5566367e28c73c31d4d0f637caaa21e7f1 (diff) | |
mb/google/rex: Enable SaGv
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index a3225ca111..f14699ff4e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -20,6 +20,8 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + register "sagv" = "SAGV_ENABLED" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, |