diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-07-04 08:44:23 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-05 10:36:33 +0000 |
| commit | 35ef2e5606b51bc28fc295e01f72c4f37779b497 (patch) | |
| tree | 86c0ab4906574e84d4dfda0ec36d4fa9f4875d0c /src/mainboard/google/rex | |
| parent | 6ce1391d1c39a049dd4e834c6f4daaec2de9938d (diff) | |
mb/google/rex/var/ovis: Set TCC to 100°C
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature for ovis.
BUG=b:270664854
TEST=Build and boot google/ovis.
Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/rex')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 4e2c00ea10..4297c8714a 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -36,6 +36,9 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" + # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) + register "tcc_offset" = "10" + # Enable CNVi BT register "cnvi_bt_core" = "true" |