diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-11-28 17:51:49 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-03 07:34:55 +0000 |
| commit | cd6a45029eaa7bea65f8d19c2254cf8b8757e970 (patch) | |
| tree | fdf5cd1ecebfe42d4c2943c8d6ae6d1ef39b3c0c /src/mainboard/google/rex/variants | |
| parent | 8ca7d26626528c4311d976ae5613668104620bcc (diff) | |
mb/google/rex: Add PCIe based SD controller
This patch adds PCIe based SD controller at RP 7 (from RP 11) with
Proto 1 schematics dated 11/30.
Additionally, added the RTD3 entries for the SD controller.
Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in
bootblock and SD_PERST_L (GPP_D02) is configured in romstage to
meet the power cycle requirement.
BUG=b:242917011
TEST=Able to build and boot Google/Rex. SD card detection is due
for the Proto 1 hardware.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/rex/variants')
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 24 |
2 files changed, 17 insertions, 9 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 1a5e3f6717..53cd05d52d 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -425,6 +425,8 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPP_E07 : [] ==> WWAN_FCPO_L */ PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 8d1d5289eb..6ec0bf2cad 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -126,15 +126,6 @@ chip soc/intel/meteorlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end #PCIE9 SSD card - device ref pcie_rp11 on - probe DB_SD SD_GL9755S - # Enable SD Card PCIE 11 using clk 2 - register "pcie_rp[PCH_RP(11)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE11 SD card device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp2 on end device ref tcss_xhci on @@ -471,6 +462,21 @@ chip soc/intel/meteorlake device generic 0 on end end end #PCIE6 WWAN card + device ref pcie_rp7 on + # Enable SD Card PCIE 7 using clk 2 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "2" + device generic 0 on end + end + probe DB_SD SD_GL9755S + end device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" |