diff options
| author | zhaojohn <john.zhao@intel.com> | 2022-12-16 09:27:19 -0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-24 23:37:56 +0000 |
| commit | 92d49da1630e94cccdfbf4ec72371f66380d5fd7 (patch) | |
| tree | 24f78a68b5b13b45c330878c4896f40dcd77e1b3 /src/mainboard/google/rex/variants | |
| parent | 387ec919d9f74947b84ed08d5eece8b2f0ca9cae (diff) | |
mb/google/rex: Enable DPTF functionality for Rex
Enable DPTF functionality for Meteor Lake Rex board.
BUG=b:262498724
TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board.
Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/rex/variants')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index cbfa49a61d..a3225ca111 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/meteorlake # S0ix enable register "s0ix_enable" = "1" + # DPTF enable + register "dptf_enable" = "1" + # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index b02999fe55..e7244cb69f 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -118,6 +118,11 @@ chip soc/intel/meteorlake }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + device generic 0 alias dptf_policy on end + end + end device ref pcie_rp9 on # Enable SSD Card PCIE 9 using clk 4 register "pcie_rp[PCH_RP(9)]" = "{ |