diff options
| author | Kapil Porwal <kapilporwal@google.com> | 2022-07-08 14:37:05 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-13 08:41:13 +0000 |
| commit | 7581730b65dab0b33b7e2eff7413780cc63c4791 (patch) | |
| tree | 30890141894a7ff0fa448da1591f294d7231269c /src/mainboard/google/rex/variants | |
| parent | a42ad2822be29ac218ef43e95ca131b20532cd30 (diff) | |
soc/intel/meteorlake: Use double digit GPIO pad numbers
Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num
e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.
BUG=b:238196741
TEST=Able to build meteorlake based google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/rex/variants')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/gpio.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c index 70f05c49b1..8ddd6cece0 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c @@ -7,19 +7,19 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* ToDo: Fill gpio configuration */ - /* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* ToDo: Fill early gpio configuration */ - /* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), }; const struct pad_config *__weak variant_gpio_table(size_t *num) |