diff options
| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2017-12-14 07:27:37 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-15 16:11:38 +0000 |
| commit | ea0aa33ea3be908b54a07984dd8072ab1b284e90 (patch) | |
| tree | 7de285b4e9aacc01b07070bd637c8b81dcc2092e /src/mainboard/google/reef | |
| parent | 91ea9f0b90546c6c085eec2e3dcfe78032dc1ad8 (diff) | |
mb/google/snappy: add reset pin for Melfas touch controller
Melfas kernel TS driver (melfas_mip4.c) will look up "ce"
GPIO during driver probe in ACPI _DSD.
But FW does not report "ce-gpios" but "enable-gpios" in _DSD.
Kernel will obtain GPIO from _CRS by index "0" without ID.
Melfas driver does not have separate condition
for MIT-410 so driver will set TS IC power off in probe.
FW now may need to add back "reset" pin in order to hack
this condition to let Melfas driver get "useless" GPIO
so TS IC power (VTSP) will be not off during driver probe by itself.
BUG=b:70149336
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef')
| -rw-r--r-- | src/mainboard/google/reef/variants/snappy/devicetree.cb | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index f40c3307c6..6adf94c1b3 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -198,6 +198,17 @@ chip soc/intel/apollolake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + # Melfas TS IC doesn't have reset pin design, current FW also not + # declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know + # "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver + # is unable to separate clear power sequence path for certain + # TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS + # by index "0" since no matched "gpio" in ACPI _DSD. + # coreboot needs to have "dummy pin" as workaround in order to let + # kernel driver grab "useless" GPIO to prevent Melfas TS driver cut + # power by driver itself. + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" register "enable_delay_ms" = "5" register "has_power_resource" = "1" |