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authorChiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>2016-08-03 14:09:33 -0700
committerDuncan Laurie <dlaurie@chromium.org>2016-08-05 18:02:50 +0200
commit44d0ddcc817708403068893a5b4f72454deea355 (patch)
tree964e7f21d63d203942732710b75b4c462b6ae5eb /src/mainboard/google/reef
parentd924fac75942db4362af5dd026ef2b0768ffb5ce (diff)
google/reef: Correct SD card pins config
SD CLK and CLK_FB needs to be pulled down by 20K. SD CD_N is active LOW, needs to be pulled up by 20K SD WP pin is not connected for uSD cards, enable writes by default by pulling low by 20K. BUG=chrome-os-partner:54866 BRANCH=None TEST=Test with uSD cards. Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef')
-rw-r--r--src/mainboard/google/reef/gpio.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 969b39296a..5eb1d1dc29 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -59,15 +59,19 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */
/* SDCARD */
- PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */
+ /* Pull down clock by 20K */
+ PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
- PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_N */
+ /* Card detect is active LOW. Pull up by 20K */
+ PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
- PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
- PAD_CFG_NF(GPIO_186, NATIVE, DEEP, NF1), /* SDCARD_LVL_WP */
+ /* CLK feedback, internal signal, needs 20K pull down */
+ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
+ /* No h/w write proect for uSD cards, pull down by 20K */
+ PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */
/* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */