diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-10-04 11:11:49 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-10-06 00:18:25 +0000 |
| commit | 6bedbd6116099f1373f6989ab43daf1164c2fbfe (patch) | |
| tree | 527c7531c670af87f95c2a2de0ff2d7d2727f08a /src/mainboard/google/reef/variants | |
| parent | 2c343386dffe747dad93c06cbef938d467f481e5 (diff) | |
soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/reef/variants')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/reef/variants/coral/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/reef/variants/coral/mainboard.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 3cd765b359..8df5873672 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -327,7 +327,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, NONE, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index e89e5b5c82..0c762c0dd3 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -327,7 +327,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, NONE, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index f99876300d..aad65f085a 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -136,9 +136,9 @@ const char *mainboard_vbt_filename(void) static const struct pad_config nasher_gpio_tables[] = { /* AVS_DMIC_CLK_A1 */ - PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* AVS_DMIC_CLK_B1 */ - PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, Tx1RxDCRx0), }; const struct pad_config *variant_sku_gpio_table(size_t *num) |