diff options
| author | Tim Chen <Tim-Chen@quantatw.com> | 2017-03-07 14:45:15 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-03-10 19:48:08 +0100 |
| commit | 327c5c60ddc14e5f466c7a2f9ac6dcfb4d9f4941 (patch) | |
| tree | 10029f44f9ebbd5fa314015ab685a0525a60c6a4 /src/mainboard/google/reef/variants | |
| parent | e392f414cd27edba78f02a5e9274126aa0a80f89 (diff) | |
mainboard/google/reef: Modify TCPU, TSR2 and TRT table
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.5_20170306.xlsx)
1. Update DPTF TCPU critical trigger point.
TCPU critical point: 105
2. Update DPTF TSR2 passive trigger point.
TSR2 passive point: 58
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 10secs.
Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
Change CPU Effect on Temp Sensor 2 sample rate to 60secs.
BUG=b:35583586
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/reef/variants')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index 0addae8fd2..79616cbe4b 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -15,7 +15,7 @@ */ #define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 103 +#define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 80 #define DPTF_CPU_ACTIVE_AC2 70 @@ -34,7 +34,7 @@ #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 58 #define DPTF_TSR2_CRITICAL 90 #define DPTF_ENABLE_CHARGER @@ -50,21 +50,21 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 30, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 2 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, #endif /* CPU Effect on Temp Sensor 1 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () |