mainboard/google/reef: Update DPTF parameters provided from thermal team

Update the DPTF parameters based on thermal test result.

1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
   CPU  passive point:61
   TSR0 passive point:120, critial point:125
   TSR1 passive point:46,  critial point:75
   TSR2 passive point:100, critial point:125

2. Update PL1/PL2 Min Power Limit/Max Power Limit
   Set PL1 min to 3W, and max to 6W
   Set PL2 min to 8W

3. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 80secs
   Change CPU Effect on Temp Sensor 0 sample rate to 120secs
   The TRT of TCHG is TSR1, but real sensor is TSR2.
   Change Charger Effect on Temp Sensor 2 sample rate to 120secs
   Change CPU Effect on Temp Sensor 2 sample rate to 120secs

BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut

Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 15 insertions, 15 deletions

diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
index 43e2e93045..afb72eba7e 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#define DPTF_CPU_PASSIVE	95
+#define DPTF_CPU_PASSIVE	61
 #define DPTF_CPU_CRITICAL	99
 #define DPTF_CPU_ACTIVE_AC0	90
 #define DPTF_CPU_ACTIVE_AC1	80
@@ -24,18 +24,18 @@
 
 #define DPTF_TSR0_SENSOR_ID	0
 #define DPTF_TSR0_SENSOR_NAME	"Battery"
-#define DPTF_TSR0_PASSIVE	48
-#define DPTF_TSR0_CRITICAL	70
+#define DPTF_TSR0_PASSIVE	120
+#define DPTF_TSR0_CRITICAL	125
 
 #define DPTF_TSR1_SENSOR_ID	1
 #define DPTF_TSR1_SENSOR_NAME	"Ambient"
-#define DPTF_TSR1_PASSIVE	60
-#define DPTF_TSR1_CRITICAL	70
+#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_CRITICAL	75
 
 #define DPTF_TSR2_SENSOR_ID	2
 #define DPTF_TSR2_SENSOR_NAME	"Charger"
-#define DPTF_TSR2_PASSIVE	55
-#define DPTF_TSR2_CRITICAL	100
+#define DPTF_TSR2_PASSIVE	100
+#define DPTF_TSR2_CRITICAL	125
 
 #define DPTF_ENABLE_CHARGER
 
@@ -50,21 +50,21 @@ Name (CHPS, Package () {
 
 Name (DTRT, Package () {
 	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 800, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
 
 #ifdef DPTF_ENABLE_CHARGER
-	/* Charger Effect on Temp Sensor 1 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+	/* Charger Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 1200, 0, 0, 0, 0 },
 #endif
 
 	/* CPU Effect on Temp Sensor 1 */
 	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 2 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -72,15 +72,15 @@ Name (MPPC, Package ()
 	0x2,		/* Revision */
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		1600,	/* PowerLimitMinimum */
-		12000,	/* PowerLimitMaximum */
+		3000,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */
 		200	/* StepSize */
 	},
 	Package () {	/* Power Limit 2 */
 		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
-		6000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMinimum */
 		8000,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */