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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-09 15:37:09 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:09:09 +0000
commit2adb50d32e8cd9c61773b1d60de545255c6a4049 (patch)
tree0c78815666d0b53bf54130e9752690ba29e61c08 /src/mainboard/google/reef/variants/pyro
parenta54bfd5e950ef108e9941a8319d0c24d786528ec (diff)
apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/reef/variants/pyro')
-rw-r--r--src/mainboard/google/reef/variants/pyro/devicetree.cb8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index f62af8a39a..1282edb9ba 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -52,12 +52,14 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
- # PL1 override 12000 mW: the energy calculation is wrong with the
+ # PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
- register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W.
- register "tdp_pl2_override_mw" = "15000"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 12,
+ .tdp_pl2_override = 15,
+ }"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"