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| author | Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> | 2016-09-08 16:11:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-12 19:49:28 +0200 |
| commit | d2e92e461db62cc8c22de5ac6925b5fdf864c0ed (patch) | |
| tree | 08075ebbc985c784fca234f1e07b20a1aabb1192 /src/mainboard/google/reef/variants/baseboard | |
| parent | 6584973bdc2ae57311f4a20041975bfac34d0d59 (diff) | |
mainboard/google/reef: Enable lpss s0ix
This setting enables lpss to power gate in S0ix.
BUG=chrome-os-partner:53876
Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/reef/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index e663787ae2..f15260b2db 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -50,6 +50,9 @@ chip soc/intel/apollolake register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_bios_config_lockdown" = "1" + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE |