mainboard/reef: add variant support to ASL code

There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.

BUG=chrome-os-partner:56677

Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

1 files changed, 39 insertions, 5 deletions

diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 05876c05f1..3265941071 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -43,11 +46,42 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <soc/intel/apollolake/acpi/sleepstates.asl>
 
-	/* Mainboard Specific devices */
-	#include "acpi/mainboard.asl"
+	/* LID and Power button. */
+	Scope (\_SB)
+	{
+		Device (LID0)
+		{
+			Name (_HID, EisaId ("PNP0C0D"))
+			Method (_LID, 0)
+			{
+				Return (\_SB.PCI0.LPCB.EC0.LIDS)
+			}
+			Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
+		}
 
-	Scope (\_SB) {
-		/* Dynamic Platform Thermal Framework */
-		#include "acpi/dptf.asl"
+		Device (PWRB)
+		{
+			Name (_HID, EisaId ("PNP0C0C"))
+		}
+	}
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include <variant/acpi/dptf.asl>
+		/* Include soc specific DPTF changes */
+		#include <soc/intel/apollolake/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <soc/intel/common/acpi/dptf/dptf.asl>
 	}
 }