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authorAaron Durbin <adurbin@chromium.org>2013-11-20 15:21:40 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-07 22:06:34 +0200
commit21565cac1b0b34c3e76c1bcd2bf933ac1313ecac (patch)
tree39fbed653a7d8c7a924ed1b948c771f256b2549c /src/mainboard/google/rambi/gpio.c
parentbaa1e382178ab6a45c5d584a88ac26c0767f8a12 (diff)
rambi: use SERIRQ pad as keyboard irq in gpio mode
The level shifting between 3.3V and 1.8V for the SERIRQ signal is not working. Instead use the SERIRQ pad as a gpio which is used as a direct IRQ signal for the keyboard interupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi. Keyboard works with associated EC change. CQ-DEPEND=CL:177189 Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177223 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4979 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/rambi/gpio.c')
-rw-r--r--src/mainboard/google/rambi/gpio.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
index dfe880a7af..76002cfd43 100644
--- a/src/mainboard/google/rambi/gpio.c
+++ b/src/mainboard/google/rambi/gpio.c
@@ -106,7 +106,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
- GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */
+ GPIO_DIRQ, /* S0-SC050 - IRQ_SERIRQ -- using for keyboard irq */
GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
@@ -213,6 +213,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+ [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
};
static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {