mb/google/rambi: Convert to use override devicetree

Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.

Change-Id: I52b71cf12a4e0b67135cfb106c3e89b00205d3bc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 100 insertions, 0 deletions

diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
new file mode 100644
index 0000000000..dc11ec8a91
--- /dev/null
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -0,0 +1,100 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 off end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 off end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end